3D Integration Technology Research Articles

A Low-profile Ultra-wideband LTCC Based Microstrip Antenna for Millimeter-wave Applications under 100 GHz

In this paper, a low profile ultra-wideband microstrip antenna is proposed for millimeter wave applications below 100 GHz to meet the demands of high data rates in the future wireless communication systems. The proposed antenna consists of a non-uniform hexagon shape radiating element on the top of 13th layer of ceramic. The proposed antenna geometry is designed using Low Temperature Co-fired Ceramic (LTCC) technology for 3D multilayer vertical integration. HFSS and CST Studio are used for design and simulation of this ultra-wideband antenna. This antenna covers a bandwidth of 33.5 GHz that ranges from 62.5 GHz to more than 96 GHz with a peak gain of 5.7 dBi, stable radiation pattern across the bandwidth, and compact size of 3.16  3.2 mm 2. The limitation of the narrow band in microstrip antenna is successfully dispensed by increasing the matching impedance bandwidth to more than 40 %. The proposed microstrip antenna is very useful for modern wireless communication systems because of its capability of covering a very wide bandwidth with favorable impedance matching and a stable radiation pattern at the considered frequency range. This antenna has another advantage in terms of the ability to be directly integrated with other RF chips using LTCC multilayer technology.

Design of a GPU Register File Using a Monolithic 3D Technique

While graphics processing units (GPUs) have been widely used to handle large amounts of data in recent years, their significant power consumption causes many usage constraints. Among the many components of a GPU, register files are critical to performance, and the crossbar network to configure them is the most significant factor in power consumption. Currently studied as a way to increase chip aggregation is 3D integration technology, like monolithic 3D (M3D) with finegrain characteristics. We suggest in this study how M3D technology can be applied to the crossbar of GPU register files to reduce power consumption. Our performance analysis shows that we obtain 40.2% and 18.9% savings in dynamic and leakage power, respectively, along with a 64.7% delay reduction.

Expecting for 3D Stacked Integration Technology

Expecting for 3D Stacked Integration Technology

Methods for Increasing the Radiation Resistance of 3D Integration Memory Modules for Aerospace Applications

Space radiation effects in electronics are significantly important during the development of devices for aerospace applications. Radiation tolerant component base significantly lag behind the commercial chips with regard to operating speed, memory capacity and etc. The issue of commercial memory use in information storage devices is especially acute in conditions of high radiation. Within the framework on development of micromodule 3D integration technology for onboard equipment for aerospace applications, the study of the radiation effects influence on the operation of commercial NAND-Flash chips and methods of counteracting these effects are carried out.

Development of Software for Measuring the Electrical Characteristics of the Information Storage Micromodule with Increased Radiation Resistance

Development of software for automation of electrical characteristics measurement plays an important role, because this approach contributes to a significant time reduction. This article discusses the development and application of software for the study of electrical characteristics of miniature data storage modules developed by 3D integration technology for aerospace applications. In outer space there are a number of problems affecting the functioning of microelectronic equipment, in particular - heavy charged particles (HCP) that can lead to both single failures and latch-up effect, which is critical for memory chips. Therefore, there is a need to check the electrical parameters, such as the response time of protection against HCP. The software is developed in LabVIEW and can be used in manual and automatic modes, what allows to improve the efficiency of the testing process. The full range of measurements can be done by one operator in a short period of time.

(Invited) Trends in 3D Markets and Technology

Driven by performance, 3D packaging with through silicon vias (TSVs) has become a reality for memory and advanced logic. New versions are emerging. High Bandwidth Memory (HBM) is one of the most important 3D IC developments in the last 10 years. In the last decade, stacked DRAM with through silicon vias has transitioned from a handful of research programs to rapidly increasing volumes. Tezzaron has been providing small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015. Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a BGA and tested before assembly on the board. The HMC has been used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC. Thermal issues were a challenge. Today Samsung and SKHynix are providing HBM stacks to the industry and Micron is expected to ship products next year. In February 2018, Samsung announced that its first “three-layer” stacked CMOS image sensors (CIS) were in mass production and found in the Galaxy S9/S9+. This follows Sony’s adoption of three-layer CIS technology one year earlier in February 2017. A third silicon layer in the form of DRAM is added to the pixel array and signal processing layers to significantly improve data readout speeds. These devices are manufactured with 3D IC technologies using TSVs, but Samsung and Sony use different design approaches. Technically speaking, Samsung’s solution is a two-layer image sensor with a stacked DRAM. Sony uses a true three-layer bonded approach. In its three-layer CIS technology, Sony places the DRAM between the pixel array die and the image processor, with all three layers interconnected using TSVs. The pixel array, DRAM, and logic wafers are manufactured with 90nm, 30nm, and 40nm processes, respectively. While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration. The technology uses a 3D face-to-face stacking process. In the process, logic die are bumped and mounted on an active interposer next to memory or die with other functions. The active interposer can contain active parts of the system, such as the platform controller hub (PCH) that manages I/O for the system. The active interposer is mounted on a package substrate with solder bumps. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW). These technologies are front-end packaging and use direct or fusion bonding. The SoIC is a wafer with logic, with our without TSVs.

Near-memory computing: Past, present, and future

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory — called near-memory computing (NMC) — more viable. Processing right at the “home” of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support

We present a novel 3D-SRAM cells using a monolithic 3D integration technology for realizing both robustness of the cell and in-memory Boolean logic computing capability. The proposed two-layer cell designs make use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, and XNOR/XOR) or enable content addressability without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes, and we evaluate the energy efficiency of our proposed design. We show that the assist techniques improve SRAM read stability by $2.2\times $ and increase the write margin by 17.6% while staying within the SRAM footprint. By the virtue of increased robustness, the cell enables seamless operation at lower supply voltages; and thereby, ensures energy efficiency. Energy delay product reduces by $1.6\times $ over standard 6T SRAM with a faster data access. When computing bulk In-memory operations, $6.5\times $ energy saving is achieved as compared to computing outside the memory system.

Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation

As a 3D integration technology, the through silicon via (TSV) has attracted increasing interest owing to the need for reducing energy consumption in devices. However, high thermal stress is induced owing to large mismatches in the coefficients of thermal expansion (CTE) between the copper via and the silicon (Si) substrate in TSVs, causing critical reliability issues such as the performance degradation of stress-sensitive devices. We proposed a novel structure, the annular-trench-isolated (ATI) TSV, as a possible solution for the reliability issues caused by thermal stress in 3D packaging technology with TSVs. The ATI TSV structure has an extra Si ring outside of the metal core. We successfully fabricated an ATI TSV with a 10-μm diameter using separate etching processes for the insulator trench and the metal core. A narrow insulator trench with a thickness of 2 μm was formed, and its aspect ratio (AR) was as high as 10. A Si ring with a thickness of 1 μm remained between the insulator layer and the metal core. In order to study the stress level of the ATI TSV, we investigated the radial and axial thermal stresses using polarized Raman spectroscopy and a simulation by the Finite Element Method. Agreement between the simulation results and the measured stress data was observed and validated the simulation model. Furthermore, we revealed that the Si substrate of the ATI TSV had a lower thermal stress level than the regular TSV. This was accomplished using the validated simulation model owing to the redistribution of stress by the Si ring in the ATI TSV.

Low latency multicasting architecture implemented using new network topology

An important service in distributed systems, as multiprocessors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. Several algorithms have been developed to implement multicasting namely the path based, and the tree based. These algorithms were able to ease the rapid saturation effect generated by such type of transmission. However, for some applications, these algorithms are not always efficient, and the multicast service might still generate the network saturation for low data loads. That's why recent studies have tried to apply these routing algorithms using a new network topology based on 3D integrated circuit technology (3DIC) . However, the 3DIC has not reached maturity because of the use of multiple number of TSV (through silicon vias).In this paper, we demonstrate the benefits of implementing adaptive multicast algorithm on a VRNOC architecture. Simulations and hardware synthesis results show that the proposed on-chip network architecture provides significant improvements in average network latency (15%) and resources (33% in number of links) than a fully 3D NOC.

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias (TSV) to electrically connect the wafers, have greatly promoted the technological advances and market development of MEMS in the past ten years. 3D integration enables heterogeneous integration of MEMS and IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems with high performance, low cost, and compact size. This paper first introduces the fundamental fabrication technologies of 3D integration, and then reviews the recent progresses of MEMS and microsystems using 3D integration and TSV technologies. MEMS-CMOS integration, TSV-based wafer level packaging, 2.5D interposer integration of MEMS are illustrated with academic achievements and commercial products by functional categorization. Finally the conclusions are made and the future trends are discussed. © 2008 Elsevier B.V. All rights reserved.

Reduction of Leakage Current Along Polyimide Layers in Wafer Level Packaging

Wafer level packaging (WLP) has become the backbone technology for chip-scale packaging and 3D integration used in compact, light-weight, and multifunctional electronic systems. Metal redistribution lines (RDL) and insulating polymer layers are the core constituents of WLP and the lateral leakage current between close-spaced RDLs have been a major concern for the electrical reliability in a dense package. In this article, it is demonstrated that Ar plasma related polyimide (PI) damage is the main cause of leakage current rather than metal residue from the RDL wet etch on the polymer surface. Through the optimization of the etch conditions after the PI descumming process by lowering RF power and raising ICP power for plasma, the leakage current of 1.6 μA is reduced to less than 5 nA. Furthermore, a model is proposed to explain the current conduction along the damaged PI layers. The results will be applicable to the fabrication of electronic devices and circuits on plastic substrate utilizing plasma-assisted processes.

PIM-WEAVER: A High Energy-efficient, General-purpose Acceleration Architecture for String Operations in Big Data Processing

The ever-growing data volume in big data era drives designers to find more efficient processor architectures both in performance and energy consumption. Among various computing patterns in big data applications, string operations are common but important parts of data processing. However, due to the consideration of generality, current general-purpose CPUs are not efficient in both performance and energy consumption when processing simple and fixed computation patterns of discrete string operations. On the other hand, moving massive data from memory to computing units through NoC, Cache hierarchies, and other memory access data paths is time-consuming and especially energy consuming. Fortunately, emerging technologies, such as Hybrid Memory Cube (HMC), enable the processing-in-memory (PIM) functionality without transferring massive data to remote processing units. In this paper, we propose PIM-WEAVER, a high-efficiency novel acceleration architecture for string processing using PIM mechanism, which is the 3D integration technology that facilitates stacking logic and memory dies in a single package. The PIM-WEAVER is implemented using such technology by integrating string processing units into the real world HMC memory. In PIM-WEAVER, the general-purpose acceleration architecture for string operation is implemented within the memory cube, which can reduce the latency of data transfer and also save energy. We also propose a full-stack solution of programming interface and control mechanism of instruction level. Our comprehensive evaluations using typical string processing algorithms from big data applications show that the PIM-WEAVER gains an average speedup of 14.74x over high-performance Intel processor, and reduces the energy consumption by 82.1% on average, with tiny area overhead.

Package Technologies for the 4th Industrial Revolution

The 4th Industrial Revolution with artificial intelligence, autonomous vehicles, robotics, and biotechnology demands power efficient computing devices such as GPU, TPU, and FPGA. To further enhance the performance, advanced System-in-Package (SiP) such as 2.5D and 3D integration technologies are needed to satisfy the high computing and power efficiency requirements. High-performance SiP systems must integrate advanced packaging technologies with both complex signal/power integrity and enhanced thermal solutions. In addition, package developers need to work closely with chip designers at a very early stage of the product development to achieve the target performance and reliability. In this Keynote, Dr. Oh, Vice President of Package Development at Samsung Electronics will start with an overview of the evolution and importance of package technology to meet the needs of emerging high-end computing platforms. Furthermore, a high-performance SiP system with a Fan Out (FO) package is introduced for power efficient mobile platforms. In addition, the extension of the FO package for high-end server applications is discussed. Finally, pros and cons of the FO package compared to 2.5D Si-interposer are discussed.

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Three-dimensional integrated circuit (3D IC) technology offers a potential breakthrough to enable a paradigm-shift strategy, called “more than Moore,” with novel features and advantages over the conventional 2D process technology. By having three-dimensional interconnections, 3D IC provides substantial wirelength reduction and a massive amount of bandwidth, which gives significant performance improvement to overcome many of the nontrivial challenges in semiconductor industry. Moreover, 3D integration technology enables to stack disparate technologies with various functionalities into a single system-in-package (SiP), introducing “true 3D IC” design. As the first physical design (PD) step, IC floorplanning takes a crucial role to determine IC’s overall design qualities such as footprint area, timing closure, power distribution, thermal management, and so on. However, lack of efficient 3D floorplanning algorithms that practically implement advantages of 3D integration technology is a critical bottleneck for PD automation of 3D IC design and implementation. 3D floorplanning (or packing, block partitioning) is a well-known NP-hard problem, and most of 3D floorplanning algorithms rely on heuristics and iterative improvements. Thus, developing complete and efficient 3D floorplan representations is important, since floorplan representation provides the foundation of data structure to search the solution space for 3D IC floorplanning. A well-defined floorplan representation provides a well-organized and cost-effective methodology to design high-performance 3D IC. We propose a new 3D IC floorplan representation methodology using corner links and partial order . Given a fixed number of cuboidal blocks and their volume, algorithmic 3D floorplan representations describe topological structure and physical positions/orientations of each block relative to the origin in the 3D floorplan space. In this article, (1) we introduce our novel 3D floorplan representation, called corner links representation , (2) we analyze the equivalence relation between the corner links representation and its corresponding partial order representation , and (3) we discuss several key properties of the corner links representation and partial order representation. The corner links representation provides a complete and efficient structure to assemble the original 3D mosaic floorplan. Also, the corner links representation for the non-degenerate 3D mosaic floorplan can be equivalently expressed by the four trees representation . The partial order representation defines the topological structure of the 3D floorplan with three transitive closure graphs (TCG) for each direction and captures all stitching planes in the 3D floorplan in the order of their respective directions. We demonstrate that the corner links representation can be reduced to its corresponding partial order representation, indicating that the corner links representation shares well-defined and -studied features/properties of 3D TCG-based floorplan representation. If the partial order representation describes relations between any pairs of blocks in the 3D floorplan, then the floorplan is a valid floorplan. We show that the partial order representation can restore the absolute coordinates of all blocks in the 3D mosaic floorplan by using the given physical dimensions of blocks.

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint

Thanks to the emerging 3D integration technology, The multiprocessor system on chips (MPSoCs) can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise (PSN) interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network (PDN) solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.

R&D status of SOI-based pixel detector with 3D stacking readout

SOFIST4 is an SOI pixel sensor designed for the International Linear Collider (ILC) vertex detector. In order to satisfy the requirements of the ILC vertex detector, the chip consists of three-stage hit-charge and hit-time memories in each 20μm×20μm pixel with 3D integration technology. The SOFIST4 chip was submitted for an MPW run in 2017, and 3D integration will be performed in 2018. In this article, the design of the SOFIST4 chip is first described. Then the 3D integration and 3D CAD technology are explained.

Cu-SiO2 hybrid bonding simulation including surface roughness and viscoplastic material modeling: A critical comparison of 2D and 3D modeling approach

Cu-SiO2 direct hybrid bonding is considered as one of the key enabling technologies for 3D integration. Previous studies showed that the main process parameters influencing the bonding quality are temperature and annealing time, as well as the mechanical stress at the Cu-Cu interface. The latter is influenced by thermo-mechanical stress introduced by the coefficient of thermal expansion mismatch of SiO2 and Cu and by geometrical effects. The modeling approach of the present study aims to shed light on the influence of surface roughness on the contact area formation between Cu pads. Roughness profiles measured with atomic-force microscopy are directly used as input for the simulation. This introduces considerable computational effort when explicitly modeled within finite element simulation. A sub-modeling technique is used to reduce the numerical cost. The common 2D modeling approach is critically compared to full 3D modeling of the surface topography. The dominant micro-mechanical temperature dependent deformation mechanisms are taken into account by continuum mechanics material models from literature. Accordingly, the stress driven instantaneous dislocation glide and the diffusion triggered climb assisted dislocation glide are taken into account by corresponding plasticity and creep material models.

Etch process modules development and integration in 3D-SOC applications

Since the challenges of maintaining the Moore's law - through traditional dimensional scaling or exploiting new materials properties - are becoming increasingly difficult, 3D integration technologies are gaining more and more attention and importance. At system level 3D-SOC solutions are of great interest, in particular those obtained through Wafer-to-Wafer (W2W) bonding due to superior overlay performance. In this paper we present the development of etch process modules for fine pitch via last interconnects realized on wafers with dielectric bonding and their integration in a packaging test chip, followed by electrical characterization.