Low latency multicasting architecture implemented using new network topology

Abstract

An important service in distributed systems, as multiprocessors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. Several algorithms have been developed to implement multicasting namely the path based, and the tree based. These algorithms were able to ease the rapid saturation effect generated by such type of transmission. However, for some applications, these algorithms are not always efficient, and the multicast service might still generate the network saturation for low data loads. That's why recent studies have tried to apply these routing algorithms using a new network topology based on 3D integrated circuit technology (3DIC) . However, the 3DIC has not reached maturity because of the use of multiple number of TSV (through silicon vias).In this paper, we demonstrate the benefits of implementing adaptive multicast algorithm on a VRNOC architecture. Simulations and hardware synthesis results show that the proposed on-chip network architecture provides significant improvements in average network latency (15%) and resources (33% in number of links) than a fully 3D NOC.