3D Inductors Research Articles

Compact and low‐loss IPD bandpass filter using 3D glass‐based redistribution layer technology

AbstractA low‐loss miniaturized bandpass filter is presented using 3D glass‐based RDL packaging technology. A new topology consisting of one modified Pi‐section and one modified T‐section is introduced to generate three transmission zeros which can achieve the high out‐of‐band rejection. A combination of 2D planar inductors and high‐Q 3D inductors is used to achieve low insertion loss and minimize the filter size. In addition, one grounded resonator at input terminal is introduced to generate an extra transmission zero in the low end. The proposed bandpass filter covering 3.3–4.2 GHz is fabricated with a compact size of 1.6 mm × 0.8 mm × 0.25 mm. It exhibits an insertion loss of less than 1.0 dB at a center frequency of 3.75GHz and a return loss of better than 14 dB. The proposed design has a 3 dB fractional bandwidth of 37.6%. Its out‐of‐band rejection is better than 20 dB at the low frequency band from DC to 2.0 GHz and better than 19 dB at the high frequency band from 5.0 to 9.0 GHz. The simulated and measured results of the proposed BPF are in reasonably good agreement.

Rapid Multi-Objective Optimization Strategy of TSV-Based 3D Inductor Using Vector Fitting and Evolutionary Algorithm

Rapid Multi-Objective Optimization Strategy of TSV-Based 3D Inductor Using Vector Fitting and Evolutionary Algorithm

A detailed study of Qdc of 3D micro air-core inductors for integrated power supplies: Power supply in package (PSiP) and power supply on chip (PSoC)

• A sensitivity analysis is carried out to understand the impact of various design parameters on the Q d c of 3D inductors. • The solenoid and the toroid inductors are implemented on a PCB of size 5 mm × 5 mm to demonstrate the research findings. • The design and analysis presented in this work help in the optimization of the performance of 3D inductors. This work presents the impact of design parameters such as the number of turns, pitch, height, conductor dimensions, etc., on the dc ratio of inductance to resistance ( L d c / R d c ) (also known as dc quality factor Q d c ) of 3D micro air-core inductors. We consider two well-known traditional inductors for the illustration: the toroid and the solenoid. We evaluate the performance of these inductors with respect to Q d c over a wide range of design parameters. To demonstrate our research findings, we have implemented the solenoid and toroid inductors on a PCB of size 5 mm × 5 mm.

System Optimization: High-Frequency Buck Converter With 3-D In-Package Air-Core Inductor

In this work, we present the analytical model of buck converter with 3D in-package air-core inductor (150 μm thick). To optimize the power efficiency at a targeted power density, models including 3D inductor and power switches are developed. Compared to 3D EM simulation, the proposed inductor model has a modeling error within 12% for the inductance calculation. With the proposed design methodology, an inductor with Q-factor up to 35 @ 300 MHz is achieved. From the system aspect, the loss breakdown in the integrated power converter is investigated. A 0.5-ratio buck converter can reach 88.5% efficiency @ 1–5W/mm2 based on the optimized inductor designs, with output voltage ranging from 0.7 V to 0.9 V and based on 28 nm CMOS.

Design, Modeling, and Analysis of a 3-D Spiral Inductor With Magnetic Thin-Films for PwrSoC/PwrSiP DC-DC Converters

This work presents the design, modeling, and analysis of a 3-D spiral inductor with magnetic thin-films for power supply applications in the frequency range of 3-30 MHz. A closed-form analytical expression for the inductance, including both air-core (winding) and magnetic-core (magnetic thin-films) contributions, of the 3-D spiral inductor structure with magnetic thin-films is derived. To validate the winding inductance model, we implement a 3-D spiral inductor with an air-core on PCB. The theoretical calculation of air-core inductance (winding inductance) is in good agreement with experimental data. The error is 5.63%. Similarly, to validate the inductance model of the magnetic-core, a 3-D spiral inductor structure with magnetic thin-films is constructed in ANSYS Maxwell; when the simulation and analytical model results of magnetic-core inductance are compared, the reported error is 5.29%. In addition, a winding AC resistance model is presented. The maximum error is 5.51%. To understand the significance of the 3-D spiral inductor structure, we perform a design space exploration (DSE). A systematic analysis is carried out to have strategically arranged inductor components (winding and core) to enhance the performance. Two important performance parameters are discussed: dc quality factor (<i>Q_dc</i>) and ac quality factor (<i>Q_ac</i>). Also, a 3-D spiral inductor structure with magnetic thin-films is characterized in ANSYS Maxwell to estimate its potential. A novel fabrication method is proposed to implement the 3-D spiral inductor with magnetic thin-films. The measured relative permeability (&#x03BC;_<i>r</i>) and magnetic loss tangent (<i>tan</i> &#x03B4;) of magnetic thin-films (Co-Zr-Ta-B), developed in-house, are used to simulate the proposed structure. The numerical solutions reveal that the 3-D spiral inductor with magnetic thin-films has the potential to demonstrate a figure-of-merit (FOM) of 1.18&#x2013;48.44&#x00D7; higher than comparable traditional inductors. The results of DSE can be extended rather easily to traditional 3D inductors such as the solenoid and the toroid to improve performance.

Design, manufacture and characterization of compact filter assemblies for radiofrequency applications

This paper presents the use of additive manufacturing in the design and fabrication of a non-planar fully 3D-printed low-pass filter. The process implements stereolithographic 3D printing and copper electroplating to produce the necessary parts and their casing. The filter we produce acts as a demonstrator: we present the possibility of constructing building blocks and combining different elements into a full assembly for system integration. We introduce the “drop-and-screw” concept, which is implemented to mount the parts into a single connectorized assembly without the need for welding. The method we propose may be suitable for building other components by simply changing the building blocks. We pay special attention to the design of the constituent parts of the filter (a 3D conical inductor and a 3D capacitor), exploring new geometries to reduce the size of the final filter prototypes. The results demonstrate the potential of additive manufacturing in the construction of high-performance RF components and assemblies, and we present a modular prototype with a high degree of reconfigurability and multifunctionality.

Design and fabrication of through-glass via (TGV) based 3D spiral inductors in fused silica substrate

Design and fabrication of through-glass via (TGV) based 3D spiral inductors in fused silica substrate

3D MEMS In-Chip Solenoid Inductor With High Inductance Density for Power MEMS Device

In this letter, we report the design and measurement of a 3D solenoid inductor that is embedded in a Si substrate and can integrate an iron core. Various inductor designs were fabricated with good structural integrity and repeatability via a CMOS-compatible MEMS fabrication process. The average inductance and quality factor peak-to-peak variation of the inductors was below 10%, which indicates that the fabrication process is repeatable. Among the inductors without iron cores, the highest quality factor (37.6 at 21 MHz) was found in a 5-turn inductor, and the highest inductance and inductance density (respectively, 86.6 nH and 21.7 nH/mm2) were found in a 20-turn inductor. Among the iron-core inductors, the 15-turn inductor had an inductance of 1063 nH and an inductance density of 354.3 nH/mm2, nearly 18 times higher than the same design without an iron core, which is the highest inductance density for a MEMS microinductor to the best of our knowledge. This type of inductor is an important component in RF MEMS and electromagnetic power MEMS devices and can improve their performance and efficiency.

Analyses of mechanically-assembled 3D spiral mesostructures with applications as tunable inductors

Mechanically-guided assembly allows the formation of 3D spiral-shaped inductors through controlled buckling, which could provide an increased quality ( Q ) factor and broadened working angle in near field communication, as compared to the planar design. An understanding of the microstructure-property relationship is essential in the design optimization of the assembly process. This work presents a theoretical model to analyze the deformations during the assembly of the 3D spiral-shaped mesostructure from a bilayer precursor that consists of a supporting ribbon and a 2D coil on its top. As validated by both the experiments and finite element analyses (FEA), this mechanics model allows accurate predictions of the assembled 3D configurations. In combination of electromagnetic simulations, we investigated the effects of various key design parameters on the final 3D configuration and the Q factor when operated as an inductor. The results suggest a significant role of the gravity effect on the assembled spiral configuration, especially for flexible coil designs with relative small cross-sectional areas or long wires. This study can serve as a reference for the design of spiral-shaped 3D inductors in different device applications.

Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor.

In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense conditions using the electroplating method was efficiently achieved and optimized. Pulsed power was used as the experimental power source and the electroplating solution was prepared with various additive concentrations. Designed control variable experiments were conducted to determine the optimized method. In the control variable experiments, the relationship of multiple experimental variables, including current density (0.25–2 A/dm2), additive concentration (0.5–2 mL/L), and different shapes of TSVs (circle, oral, and square), were systematically analyzed. Considering the electroplating speed and quality, the influence of different factors on experimental results and the optimized parameters were determined. The results showed that increasing current density improved the electroplating speed but decreased the quality. Additives worked well, whereas their concentrations were controlled within a suitable range. The TSV shape also influenced the electroplating result. When the current density was 1.5 A/dm2 and the additive concentration was 1 mL/L, the TSV filling was relatively better. With the optimized parameters, 500-μm-deep TSVs with a high aspect ratio of 10:1 were fully filled in 20 h, and the via density reached 70/mm2. Finally, optimized parameters were adopted, and the electroplating of 1000-μm-deep TSVs with a diameter of 100 μm was completed in 45 h, which is the deepest and smallest through which a three-dimensional inductor has ever been successfully fabricated.

3D IPD on Thru Glass Via Substrate using panel Manufacturing Technology

Abstract As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

INDUCTORS USING 2.5D SILICON INTERPOSER WITH THICK RDL AND TSV-LAST TECHNOLOGIES

Abstract Silicon interposers represents an interesting alternatives to organic packages for the fabrication of complex System In Package (SIP) modules especially for RF application. Among the advantages of this technology are the capability to fabricate fine-pitch redistribution layers and also to embed high quality passive components inside the interposer. This allows the passive components to be very close to the active chips resulting in highly integrated and high performance systems. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of various design of planar and 3D inductor devices fully compatible with the realization of a silicon interposer that is used to host an RF transmitter system operating in the 0.4 to 1 GHz frequency range. The inductors are built using two thick levels of copper RDL, on both sides of a high resistive silicon substrate and connected by through silicon via-last (TSV-last). This later doesn't require additional metallization to be realized. A dedicated test vehicle was designed to study various inductor types including planar spirals, 3D solenoids and 3D torus. To facilitate the design work, parameterized cells were built for each type of inductors. The structures geometry are designed and optimized, using electromagnetic simulator, to target inductance values in the range of 0.5 to 10 nH while addressing a quality factor greater than 20. The second part of the paper focuses on the process used to build the test vehicle, especially the realization of thick copper RDL layers on both sides of the interposer silicon wafer and the TSV-last module. Physical and DC electrical characterizations are presented to assess the integrity of the individual technology modules like thick copper RDL and TSV. The last part of the work is dedicated to the electrical characterization of the inductor devices in the targeted RF frequency range. Experimental results are presented and discussed in order to give some insight on the impact of the different design parameters on the performances of the inductors.

A Secure Tunable LNA Design for Internet of Things

Abstract This paper describes the design of through-silicon via (TSV)-based inductors for a secure tunable low-noise amplifier (LNA) in Internet of Things (IoT) devices. To improve cybersecurity infrastructure, we designed a tunable LNA with hardware security. Our secure design for tunable LNA uses a ring oscillator-based physically unclonable function (PUF) circuit. For the 3D inductors, we use ferromagnetic materials to achieve high inductance with a good quality factor.

High performance 3D printed electronics using electroless plated copper

This paper presents design and performance validation of 3D printed electronic components, 3D toroidal air-core inductors, fabricated by multi-material based Fused Deposition Modelling (FDM) 3D printing technology and electroless copper plating. Designs of toroidal inductor is investigated with different core shapes and winding numbers; circular and half-circular cores with 10 and 13 turns of windings. Electroless plated copper thin film ensures 3D printed toroidal plastic structures to possess inductive behaviors. The inductance is demonstrated reliably with an applied source frequency from 100 kHz to 2 MHz as designs vary. An RL circuit is utilized to test the fabricated inductors’ phase-leading characteristics with corresponding phase angle changes.

3D TSV-based Inductor Design for a Secure Internet of Things

Abstract This paper describes the design and modeling of through-silicon via (TSV)-based high-density 3D inductors for Internet of Things (IoT) applications and presents some possible challenges for TSV-based inductors in IoT applications. For cybersecurity infrastructure, we designed IoT with hardware security in mind. We provide a secure design for Internet of Things based on secure 3D inductors and then show case studies of high-density RF packages with TSV-based inductors that require hardware security, such as military applications. We use ferromagnetic materials to achieve high inductance with good quality factor.

Simple and accurate inductance model of 3D inductor based on TSV

The implementation of on-chip inductors in integrated circuit application remains a challenge to satisfy the requirements of high Q-factor, small area consumption, limited parasitic coupling, ease of layout, and manufacture. Fortunately, the emerging technology of through-silicon via (TSV) offers a possible solution to this issue by developing 3D inductor with solenoid architecture. A simple and accurate inductance model of 3D inductor based on TSV is exploited by analytical method. The inductance results obtained from the proposed model and finite element method exhibit good agreement with various design parameter ranges, and the errors between the results of the proposed analytical model and measurement are <7.5%, which verifies the accuracy of the model.

Design of TSV-based Inductors for Internet of Things

This paper describes the design of a Through Silicon Via based high density 3D inductors for Internet of Things (IoT) applications. We present some possible challenges for TSV-based inductors in IoT applications. The current trend towards Internet of Things (IOT), System in Package (SiP) and Package-on-Package (PoP) requires meeting the power requirements of heterogeneous technologies while maintaining minimum package size. 3-D chip stacking has emerged as one of the potential solutions due to its high density integration in a 3D power electronics packaging regime. As an integral part of many power electronics applications, TSV-based inductors are becoming a popular choice because of their high inductance density due to the reduced on-chip footprint compared to conventional planar inductors. Depending on the requirement, values of these inductors could range from a few nanohenries to hundreds of microhenries. Small inductors with a high quality factor are mainly used for RF filter applications, whereas large inductors are used in power electronics packaging. For high inductance it is necessary to use ferromagnetic materials. A conventional ferromagnetic metal core like nickel could offer high permeability, which can help to boost the inductance. However, the magnetic field lines within a metal core induce eddy current which can have multiple adverse effect in power electronics packaging. For example, it has long been known that the current can increase the resistance in transformer winding [1]. Eddy current can also heat up the core of the inductor which makes the heat sink process in 3D packaging even more challenging. One way to decrease the eddy current, is to pattern and laminate the core block into multiple segments orthogonal to the direction of the magnetic field line [2]. Another method is to increase the resistivity of the core material so that the eddy current is limited to a very small magnitude [3].

Tunable High-Q TSV Inductor Packaging with MEMS

In this paper, we present a Through-Silicon-Via (TSV)-based 3D tunable inductor implementation for RF applications. The proposed inductor structure uses MEMS (Micro Electro-Mechanical Systems) switches to vary inductance by activating and deactivating the switches. MEMS-based switches are used to offer high isolation in the off state. The tunable inductor is tested within an LNA circuit for variation in off-state leakage resistance. Detailed 3D full wave simulation results are presented for different cellular frequency bands.

Multi‐layer on‐chip inductor for 10–100 GHz frequency applications

A multi-layer inductor is proposed to achieve high inductance with moderate Q-factor values. The development of integration of devices technology in radio-frequency (RF) has increased the importance of on-chip inductors. In the literature, the planar inductor, the three-dimensional (3D) inductor with constant width and the 3D inductor with variable width are reported. Using the basic concept of multi-layer technology in very large-scale integration (VLSI) system design and considering lambda rules, the proposed inductor is designed. The inductance of the proposed inductor is nearly 37–45% higher compared with reported inductors with a moderate quality factor. This inductor is realised using 180 nm scale technology with an area of cross-section 10 × 10 µm2. Results are presented using the IE3D EM field solver with the help of series RL and shunt RC lumped Pi model.

A wideband active feedback LNA with a modified 3D inductor

A modified miniature 3D inductor to implement a fully-integrated feedback wide band amplifier in a standard SiGe low cost 0.35 μm process is presented. According to the measurement results, the proposed technique achieves a 40% area reduction with minor performance degradation over the same circuit implemented with conventional inductors. The circuit provides a gain from 14 dB to 7 dB in the band between 3.1 GHz to 10.6 GHz. In the same band the noise figure (NF) varies from 2.9 dB to 4 dB. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1561–1567, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25283