Design of TSV-based Inductors for Internet of Things

Abstract

This paper describes the design of a Through Silicon Via based high density 3D inductors for Internet of Things (IoT) applications. We present some possible challenges for TSV-based inductors in IoT applications. The current trend towards Internet of Things (IOT), System in Package (SiP) and Package-on-Package (PoP) requires meeting the power requirements of heterogeneous technologies while maintaining minimum package size. 3-D chip stacking has emerged as one of the potential solutions due to its high density integration in a 3D power electronics packaging regime. As an integral part of many power electronics applications, TSV-based inductors are becoming a popular choice because of their high inductance density due to the reduced on-chip footprint compared to conventional planar inductors. Depending on the requirement, values of these inductors could range from a few nanohenries to hundreds of microhenries. Small inductors with a high quality factor are mainly used for RF filter applications, whereas large inductors are used in power electronics packaging. For high inductance it is necessary to use ferromagnetic materials. A conventional ferromagnetic metal core like nickel could offer high permeability, which can help to boost the inductance. However, the magnetic field lines within a metal core induce eddy current which can have multiple adverse effect in power electronics packaging. For example, it has long been known that the current can increase the resistance in transformer winding [1]. Eddy current can also heat up the core of the inductor which makes the heat sink process in 3D packaging even more challenging. One way to decrease the eddy current, is to pattern and laminate the core block into multiple segments orthogonal to the direction of the magnetic field line [2]. Another method is to increase the resistivity of the core material so that the eddy current is limited to a very small magnitude [3].