3D Chip Stacking Research Articles

Hybrid Bright-Dark-Field Microscopic Fringe Projection System for Cu Pillar Height Measurement in Wafer-Level Package.

Cu pillars serve as interconnecting structures for 3D chip stacking in heterogeneous integration, whose height uniformity directly impacts chip yield. Compared to typical methods such as white-light interferometry and confocal microscopy for measuring Cu pillars, microscopic fringe projection profilometry (MFPP) offers obvious advantages in throughput, which has great application value in on-line bump height measurement in wafer-level packages. However, Cu pillars with large curvature and smooth surfaces pose challenges for signal detection. To enable the MFPP system to measure both the top region of the Cu pillar and the substrate, which are necessary for bump height measurement, we utilized rigorous surface scattering theory to solve the bidirectional reflective distribution function of the Cu pillar surface. Subsequently, leveraging the scattering distribution properties, we propose a hybrid bright-dark-field MFPP system concept capable of detecting weakly scattered signals from the top of the Cu pillar and reflected signals from the substrate. Experimental results demonstrate that the proposed MFPP system can measure the height of Cu pillars with an effective field of view of 15.2 mm × 8.9 mm and a maximum measurement error of less than 0.65 μm.

Enhanced Mechanical Properties with Ag Addition in Electroplated Ni-Sn Solder Joints: Sub-10 Micron Bond Thickness

Keywords: Micro-bump; Microstructure; Intermetallic compounds; Mechanical properties; thermocompression bondingThe advancement of electronic devices has garnered more extensive attention towards three-dimensional integrated circuit (3D-IC) technology due to microbump size reduction and increased power density. Microbumps play an important role in driving the development of this technology, especially in 3D chip-stacking involving multiple reflow processes. The reduction in microbump height spotlights the presence of intermetallic compounds (IMCs). In comparison to traditional ball grid array (BGA) solder joints, microbumps with smaller solder volumes exhibit a predominant fraction of IMCs at solder joints, especially with microbump dimensions potentially shrinking to less than 10 micrometers.The interface reaction within confined spaces has become a critical concern. Mechanical properties will be dominated by IMC properties rather than solder characteristics. In conventional Cu/Sn/Cu solder joints, grain coarsening and prolonged reflowing times, which result in IMC collisions from opposing substrates, forming columnar grains with a uniform orientation, make the solder joint less reliable. Furthermore, the Cu3Sn layer in Cu/Sn/Cu microbumps presents another challenges, indicating the formation of Kirkendall voids, increasing the risk of brittle interface fractures.This study investigates the mechanical reliability and microstructure of two sub-10um sandwiched structures: Cu/Ni/Sn/Ni/Cu and Cu/Ni/Sn-3.5Ag/Ni/Cu. In the 3D-IC manufacturing process, solder joints will experience multiple reflow processing. Different reflow heat treatment process to achieve different fractions of Ni3Sn4 IMCs were performed on both sandwiched structure. Despite the formation of internal voids due to volume shrinkage in Ni/Sn solder joints, the addition of silver in the solder, forming Ag3Sn, effectively fills these voids. The long-time reflowed sample showed outstanding mechanical properties via the addition of silver in solder. In this study, the influence of silver addition on the microstructure and mechanical properties of the overall joints under identical reflow conditions, the fracture path observation after shear test were investigated. The growth mechanism of Ag3Sn and its distribution in the solder would be further explored and addressed. Figure 1

Preface

The 2024 4th International Conference on Advanced Materials and Mechatronics (ICAMM 2024) was held via virtual form in Xi’an, China from May 10th to 12th, 2024. Previous conferences in the past three years of this series have been successfully held and it was agreed to hold the conference once a year, with the aim to establish and develop a constant international collaboration. In recent years, interest in advanced materials and mechatronics has been flourishing all over the globe due to both theoretical and practical requirements. Considering the trend, the fourth conference of ICAMM series was organized in order to provide an international academic forum for developing research cooperation and to promote research and other academic activities in related fields. We entertained about 80 participants at ICAMM 2024 and arranged various speeches and presentations which cover a wide range of topics related to the Conference theme. Many scholars and researchers all over the world have contributed to the emerging technology and application of advanced materials and mechatronics. The wonderful keynote speeches included Semiconductor Lighting and Display: Design and Manufacturing Technology for High Efficiency GaN-based LED Chips (by Prof. Shengjun Zhou, Wuhan University, China), Materials, Processing and Reliability of Low Temperature Bonding in 3D Chip Stacking (by Prof. Liang Zhang, Xiamen University of Technology, China), Monitoring Applications of Electronic Devices in the Shipbuilding Industry (by Assoc. Prof. Fengming Du, Dalian Maritime University, China), and Addictive Manufacturing and Intelligent Processing Control of Advanced Metal Materials (by Prof. Kun Li, Chongqing University, China). ICAMM 2024 has been endorsed and supported by many national and international engineering-related universities and organizations and was a complete success. The topics of papers collected and undergone rigorous peer review in the Proceedings of ICAMM 2024 can be classified as follows: Semiconductor Materials, Mechanics of Materials, Material Forming Process and Equipment, Advanced Electromagnetism, Laser Physics and Technology, Irradiation electronics, etc. Last but not the least is our gratitude. We would like to express our sincere thanks to all the keynote speakers, authors, committee members for the success of the Conference, which has given rise to this present volume of selected papers. We would also like to acknowledge the staff of Journal of Physics: Conference Series for their effective work to make this Proceedings published. The Committee of ICAMM 2024 List of Committee Member is available in this Pdf.

Bidirectional interlayer cooling of 3D chip stack for temperature uniformity enhancement and hotspot mitigation

In this work, bidirectional interlayer cooling with both enhanced temperature uniformity and low flow resistance is proposed for effective 3D chip stack thermal management. Staggered uniform micropin fins and curved entrance and exit regions are elaborately designed. Experimental and numerical studies are carried out to investigate the cooling characteristics under different Reynolds numbers and heat fluxes. In comparison with common interlayer cooling solutions, counter-flow arrangement is achieved between the layers and vertical heat transfer within the chip stack is utilized. Heat fluxes of 300 W/cm2 and 100 W/cm2 are dissipated in the hotspot and background zones respectively. Total thermal resistance of 0.18 K/W is obtained. The maximum decrease in temperature difference is up to 66.2%. Both thermal resistance and coefficient of performance (COP) are considered and compared with the results from previous studies for comprehensive performance evaluation. The maximum COP of 11,523 is reached. The thermal and hydraulic performance advantages of the present design can be verified. The bidirectional interlayer cooling offers new potential for thermal management of 3D chip stack.

Transition-free indirect bonding towards 3D multi-layer glass stacking

Optical and photonic devices comprised of fused-silica glass portfolios play an important role in astronomical detections, which requires the bonding interfaces to own robust mechanical properties and less optical loss. Indirect bonding lowers the difficulty of the bonding process than direct bonding by introducing the non-negligible intermediate or transition layers but will inversely diminish the optical properties. In this study, a transition-free indirect bonding (TFB) strategy was developed to realize glass bonding with hard-to-distinguished interfacial boundary. In the process, the oxygen plasma activation was applied to reconstruct the glass surface. Owing to the produced chemical sites with the plasma surface activation, multiple paths could be provided for surface and interface reactions than conventional indirect bonding method hydroxide-catalyzed bonding (HCB). These adequate reactions constructed a whole and uniform Si-O network crossing the bonding interfaces, which was free of transition boundary between the interface and bulk substrates. The uniform and non-transition interface performed higher bonding strength and excellent optical transmittance with less loss than HCB. Based on the TFB strategy, multilayer chips were combined together enabling a 3D multi-layer chip stacking with low transmittance loss and stable mechanical structure for state-of-the-art optical applications in astronomical detection, laser instruments, and optical sensors.

Microstructure and Shear properties of Sn–xZn Transient Liquid Phase Bonding in 3D-Chip Stacking Packaging

Microstructure and Shear properties of Sn–xZn Transient Liquid Phase Bonding in 3D-Chip Stacking Packaging

Transient liquid phase bonding (TLPB) of Cu to Cu using Sn interconnect solder reinforced by submicron Al particles

As an intermediate layer of transient liquid bonding, Sn interconnect solder is widely used in 3D chip stack interconnection due to its lower cost and excellent wettability. This study focuses on the effect of submicron Al particles on the interfacial microstructure and properties of Sn interconnect solder. Adding submicron Al particles efficiently restrained the growth of interfacial IMC and improved the wettability and mechanical properties of Sn interconnect solder, but it has little effect on the melting characteristics. When the 0.3 wt% submicron Al particles are added into Sn interconnect solder, the spreading area, shear strength and microhardness were improved by 69.5 %, 45.6 % and 20 %, respectively. Based on the content optimization of Al particles, the microstructure evolution and bonding strength of Sn-0.3Al interconnect solder as transient liquid bonding intermediate layer at different bonding times were studied. It was found that the growth rate of IMC and the number of voids in Sn-0.3Al TLPB joints were lower than those in the Sn TLPB joints. The bonding strength of TLPB joints increased with the increase of bonding time, and the bonding strength of Sn-0.3Al TLPB joints was always higher than that of TLPB joints without submicron Al.

(Invited, Digital Presentation) Development of 3D-Stacked Artificial Retina Chip with 3DIC/TSV and Advanced Packaging Technology

3DIC/TSV is the most promising candidate for high-performance and low-power computing devices. They have many advantages such as short wiring length, small pin capacitances, high packing density, ultra-parallel operation. Among several types of 3D-IC technologies, multiple chips-to-wafer (MCtW) stacking can stack known-good chips fabricated with different technologies and sizes, leading to a true 3D heterogeneous system. We have developed a fully implantable retinal prosthesis with a 3D-stacked artificial retina (AR) chip. In the 3D-stacked AR chip, the photoreceptor chip and stimulus current generator with image processing circuits are vertically stacked and electrically connected by many TSVs. Furthermore, advanced packaging technology like FOWLP is being developed to implement multiple AR chips in a flexible substrate to obtain a wide viewing angle. This leads to small chip size, lightweight, large fill-factor, high resolution, and high quality of life patients.

3 Paths to 3D Processors

A crop of high-performance processors is showing that the new direction for continuing Moore's Law is all about up. Each processor generation needs to perform better than the last, and at its most basic, that means integrating more logic onto the silicon. But there are two problems. The first is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The second is that individual chips have reached their size limits. Photolithography tools can pattern an area no larger than about 850 square millimeters, which is about the size of a modern server GPU. ▣ One answer has been to place two or more pieces of silicon side by side in the same package and stitch them together using millimeters-long, dense interconnects, so they can effectively act as a single unit. This so-called 2.5D scheme, enabled by advanced packaging technology, is already behind several top processors, which are now composed of several functional “chiplets” rather than a single IC. ▣ But to sling truly huge volumes of data around as if it were all on the same chip, you need even shorter and denser connections, and that can be done only by stacking one chip atop another. Connecting two chips face-to-face in a 3D scheme can mean making hundreds or thousands of micrometers-long connections per square millimeter. These short, dense connections let data zip from one piece of silicon to another almost as rapidly and with as little energy as if the two were one chip. ▣ It's taken a lot of innovation to get it to work. Engineers had to figure out how to keep heat from one chip in the stack from killing the other, decide what functions should go where and how they should be manufactured, keep the occasional bad chip from leading to a lot of costly dud systems, and deal with the resulting added complexities of doing all that at once. ▣ Here are three examples that show not just how 3D chip stacking is done but also what it's good for.

Effect of Thermal Cyclic Loading on Stress-Strain Response and Fatigue Life of 3D Chip Stacking Structure

The thermo-mechanical reliability of IMCs (Ni3Sn4, Cu3Sn, Cu6Sn5) solder joints and Sn-3.9Ag-0.6Cu solder joints was investigated systematically in 3D chip stacking structure subjected to an accelerated thermal cyclic loading based on finite element simulation and Taguchi method. Effects of different control factors, including high temperature, low temperature, dwell time of thermal cyclic loading, and different IMCs on the stress-strain response and fatigue life of solder joints were calculated respectively. The results indicate that maximum stress-strain can be found in the second solder joint on the diagonal of IMC solder joints array; for Sn-3.9Ag-0.6Cu solder joints array, the corner solder joints show the obvious maximum stress-strain, these areas are the crack propagated locations. The stress-strain and fatigue life of solder joints is more sensitive to dwell temperature, especially to high temperature; increasing the high temperature, dwell time, or decreasing the low temperature, can reduce the stress-strain and enlarge the fatigue life of solder joints. Finally, the optimal design in the 3D-IC structure has the combination of the Cu6Sn5/Cu3Sn, 373 K high temperature, 233 K low temperature, and 10 min dwell time. The fatigue lives of Sn-3.9Ag-0.6Cu under 218–398 K loading in the 3D assembly based on the creep strain are 347.4 cycles, which is in good agreement with experimental results (380 cycles).

Survey on Near-Data Processing: Applications and Architectures

One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption. In this context, Near-Data Processing (NDP) proposals have started to gain acceptance as an accelerator device. Such proposals alleviate the memory bottleneck by moving instructions to data whereabouts. The first proposals date back to the 1990s, but it was only in the 2010s that we could observe an increase in papers addressing NDP. It occurred together with the appearance of 3D-stacked chips with logic and memory stacked layers. This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures. We also introduce a new taxonomy to classify such architectural proposals according to their data distance.

Interfacial reaction, shear behavior and microhardness of Cu-Sn TLP bonding joints bearing CuZnAl powder for 3D packaging

The process of transient liquid phase bonding to form intermetallic compound solder joints can effectively achieve 3D chip stack interconnection. However, there are a large number of void defects in IMC solder joints due to the rapid reaction between elements, which reduces the reliability of the chip stack interconnection. In this study, the interfacial reaction, shear behavior and microhardness of CuSn TLP bonding joints were investigated by adding 0.5 wt% CuZnAl powder into the pure Sn interconnect solder. Adding CuZnAl powder can remarkably retard the growth of intermetallic compound and voids in the bonding joints, which is attributed to the fact that CuZnAl powder can reduce the concentration gradient of Cu in the interface region. Compared with the Cu-Sn-Cu bonding joints, the shear strength of composite bonding joints was increased by 12%–19.7%, and the microhardness of composite bonding joints was also improved.

Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits

3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data. If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique. With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine where the energy is really confined in such 3D circuits, before find solutions to limit pollutions coming from electro-magneto -thermal phenomena or background noises.

Three influential factors on colloidal nanoparticle deposition for heat conduction enhancement in 3D chip stacks

Thermal management is one of the major challenges facing the development of three-dimensional (3D) chip stacks. Recently, experimental studies have shown that neck-based thermal structure (NTS) between chip layers formed by drying of colloidal suspension in cavity filled with micro-size particles can improve the vertical heat conduction threefold. However, a deep understanding of the mechanisms of neck formation and its influence on heat conduction is still lacking. In this paper, we numerically study the effects of three parameters, i.e., initial nanoparticle concentration, drying temperature and chip surface wettability on neck formation between filler particles and on the resulting heat conduction of the NTS. With increasing nanoparticle concentration, the size and number of necks increase, resulting in an increased effective thermal conductivity (ETC) of NTS. The drying temperature is found to have only little influence on the ETC of resultant NTS, while the neck size and spatial distribution become more uniform at higher drying temperature. When reducing the wettability of the top and bottom surfaces of the cavity, the necks shrink in size until completing evacuating at the top and bottom layers, while the size of the necks between filler particles in the middle height of the cavity expands slowly. In consequence, the ETC of NTS drops at an increasing rate. Being able to reveal the underlying multiple mechanisms of two-phase flow, phase change and heat transport, the current numerical study suggests optimal values for the deposition process, with initial nanoparticle concentration over 0.8%, a drying temperature of 60°C and a uniform contact angle of 30° for practical production of NTS.

Design, Fabrication, and Comparison of 3D Multimode Optical Interconnects on Silicon Interposer

While conventional silicon photonic (SiP) waveguides achieve high data rates with low loss, they can only be placed on top of the chip surfaces horizontally. In this article, we present a design approach for multimode chip-to-chip interconnects with similar low-loss and high-bandwidth density properties as SiP waveguides. The state-of-the-art fabrication of optical through silicon via (OTSV) requires conventional back end of line (BEOL) processing with an additional step: metal coating lowers the loss of air-filled TSVs. Alternatively, the TSV is converted into a polymer waveguide by filling of low-loss polymer (Ormocore) to achieve <0.1 dB optical power loss over 380 μm distance. A 3D multimode optical interconnect is measured at 40 Gbit/s with the bit error rate (BER) <10−12 at 1550 nm wavelength. The proposed solution supplies a new path for 3D integration of optical waveguides capable of delivering high-speed data within 3D stacked chips.

(Invited) Application of Three Dimensional Chip Stacking Technology for Fully Depleted Silicon-on-Insulator Quantum Beam Imager

Requirements of a quantum beam imager such as a vertex detector in high energy physics experiment are intelligent functions which are realized by embedding memories of quantum beam hit-position, hit-charge, and hit-timing in a pixel with keeping small pixel size to achieve high spatial resolution. To satisfy the requirements, circuit layer stacking on a sensor, i.e., three dimensional (3D) technology, has been widely studied and proposed. The Silicon-on-Insulator (SOI) sensor is one of the 3D sensors because the circuits in the top silicon layer is on the sensors of the bottom silicon substrate. The circuits and sensors are electrically connected by submicron W filled vias through the buried oxide (BOX), which are called as through BOX vias (TBV). Thus, the SOI sensor has extremely higher fill factor than the bulk-CMOS sensor. In order to achieve more intelligent functions in the pixel, however, the pixel size by using the simple SOI technology is large to get the required spatial resolution. Therefore, multiple circuit layer formation by chip stacking technology is adopted. In this chip stacking, a fine pitch micro-bump technology with two-tile face-to-face stacking is employed because of the simplest 3D structure. The target of micro bump diameter and spacing are 2.5 μm and 5 μm, respectively. The SOI 3D chip stacking process is starting with the base chips which are fabricated by an 8 inch 0.2 μm fully depleted SOI pixel sensor process with five metal layers. After the metal 5 etching, an oxide film is deposited and planarized by chemical mechanical polishing (CMP). W-filled vias to a under bump metal is formed at bump formation areas. After the under bump metal deposition and patterning, metal bumps are formed. Then, two chips which are lower and upper chips are aligned and bonded face-to-face at 200℃ followed by adhesive injection. To make bonding pads on the upper chip, the upper chip handle silicon is etched until exposing the BOX and TBV by wet solution. TBV can easily connect between circuits in the upper chip and the bonding pad metal without any through silicon via (TSV) process. This is the most superior point to use the FD-SOI pixel sensor in 3D structure. The TBV size is around 0.3 μm which is much smaller than a conventional TSV whose size is around 5 μm by using the most advanced technology. In addition, this TBV can be used as interconnections between multiple chips without any TSV. Finally, bonding pad and passivation formation are done. For micro bump formation, a gold bump was utilized because the gold is oxidation-resistant metal. The micro gold bump was fabricated by two methods. One is a cone shaped gold bump manufactured by a gold nanoparticle deposition with a photoresist lift-off technique [1]. The cone shaped gold bump with 2.5 μm in diameter and 2.5 μm in height are successfully formed on the under bump metal layer. Because of the nanoparticle deposition, the gold bump is easier to deform by the bonding. Thus, the collapsibility allows low stress to the die and high reliable junctions. It is also confirmed that the bump resistance is approximately 0.25 Ω/bump from daisy chain measurement. The other is a gold cylindrical bump using a combination of inverse-tapered photoresist and low incident angle sputtering [2]. Because of narrowing at the top, lower pressure to collapse between the bumps is required than the gold cone bumps. This may also improve bump yield and reliability. 0.37 Ω/bump of the bump resistance is obtained by the gold cylindrical bumps. Using the FD-SOI 3D chip stacking technology with the cylindrical bump, the pixel sensor designed for the International Linear Collider (ILC) vertex detector called SOFIST was fabricated and the chip photo is shown in the figure. In SOFIST, hit-position, hit-charge, and hit-time memories are embedded in each pixel by the 3D micro bump bonding with 20 mm pixel size. Owing to the removal of the handle silicon of the upper chip, the patterns of the lower chip can be seen through the upper chip oxide. The green patterns close to bonding pads are backsides of silicon layer in the upper chip. As shown in the figure, our 3D process technology is successfully introduced in FD-SOI quantum beam imager.

A study on substrate noise coupling among TSVs in 3D chip stack

A study on substrate noise coupling among TSVs in 3D chip stack

EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory

For future exascale computing systems, ultra-high-density memories would be required that consume low power to process massive data. Of the various memory devices, 3D-stacked DRAMs using TSVs are a perfect solution for this purposes. In addition to providing high capacity, these provide functional flexibility to the computing system by attaching a logic die in each 3D-stacked DRAM chip. However, the high capacity 3D-stacked DRAMs suffer from a significant loss of refresh power, which is solely required to maintain data. Although various schemes have been proposed to mitigate this issue, they cannot be adopted by commercial products due to compatibility issues. To tackle this issue, we propose EXTREME, which effectively reduces the refresh power of 3D-Stacked DRAMs. In order to retain the compatibility with OS, a simple page table manager is implemented at the logic die of 3D-stacked DRAM devices, which pins the page table to a specific memory space. The experiment results demonstrate that this reduces the refresh power at idle time by up to 98 percent with 16 KB of SRAM (static RAM) and 64 KB of DRAM register overhead for a 2 GB 3D-stacked DRAM device.

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

Study of Seed-Layer Stability on Copper Electrolytic Bath

For years, the effectiveness of the Damascene process has allowed the semiconductor industry to successfully keep the pace with the aggressive scaling of Moore’s law. However, ever increasing costs have raised the need for alternative technologies bringing advantages in terms of performance gain, time to market and cost competitiveness. Thus, 3D chip stacking technologies have now become a field of extensive research [1-2]. The today improvements are mainly devoted on the current process optimization or the development of new methods to elaborate barriers, seed-layers and fillings compatible with technological advances and the more and more aggressive via aspect-ratio [3]. Generally made in copper by CVD, PVD, ALD or electrografted technics, the seed-layer plays an important role during the via filling. Its principal criteria are to be uniform in term of thickness and continuous to ensure a good electrical contact during the electrochemical process [4]. During the filling process, the wafers and thus the seed-layer are first pre-wetted using DI water or etching solutions and then immerged in the copper bath. Traditionally an idle time is maintain before applying the current density, to favour the species exchange. However, few studies have an interest for the reaction during this idle time and in more general consideration for the copper seed-layer stability on the copper electrolytic bath. Hence, the copper seed-layer is dissolved in the plating bath due to electrochemical reaction with the oxygen dissolved in the bath [5-7]. In this research work, the stability of the seed-layer and its dissolution rate are studied combining in-situ and ex-situ technics (figure 1). Open circuit potential versus time is an interesting approach for this study, allowing direct information on the surface modification during the idle time. Quartz microbalance measurements complete the analyses, giving direct information of weigh lost resulting from dissolution. As ex-situ characterization technics, SEM-EDS, XPS and RBS measurement were performed to characterize the surface states and the chemical composition after the idle time. Several parameters are particularly highlighted as the bath composition and its concentration and the rotation rate of the substrate. [1] T.P. Moffat, D. Wheeler et al., IBM J. Res. Dev., 49, 19 (2005) [2] P.M. Vereecken, R.A. Binstead, H. Deligianni, P.C. Andricacos, IBM J. Res. Dev, 49, 3 (2005) [3] M. Datta, Electrochemical processing technologies and their impact in microelectronic packaging in Microelectronic Packaging, edited by M. Datta, T. Osaka and J.W. Schultze, CRC Press edition (2005) [4] Part II Chip metallization in Microelectronic Packaging, edited by M. Datta, T. Osaka and J.W. Schultze, CRC Press edition (2005) [5] R. Schumacher et al, J. Electroanal. Chem. 219 (1987) 311-3174 [6] K.Y. Electrochimica Acta, 38, 14 (1993) 2121-2127 [7] A.G. Zelinsky et al, Corrosion Science 46 (2004) 1083–1093 Figure 1