3 Paths to 3D Processors

Abstract

A crop of high-performance processors is showing that the new direction for continuing Moore's Law is all about up. Each processor generation needs to perform better than the last, and at its most basic, that means integrating more logic onto the silicon. But there are two problems. The first is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The second is that individual chips have reached their size limits. Photolithography tools can pattern an area no larger than about 850 square millimeters, which is about the size of a modern server GPU. ▣ One answer has been to place two or more pieces of silicon side by side in the same package and stitch them together using millimeters-long, dense interconnects, so they can effectively act as a single unit. This so-called 2.5D scheme, enabled by advanced packaging technology, is already behind several top processors, which are now composed of several functional “chiplets” rather than a single IC. ▣ But to sling truly huge volumes of data around as if it were all on the same chip, you need even shorter and denser connections, and that can be done only by stacking one chip atop another. Connecting two chips face-to-face in a 3D scheme can mean making hundreds or thousands of micrometers-long connections per square millimeter. These short, dense connections let data zip from one piece of silicon to another almost as rapidly and with as little energy as if the two were one chip. ▣ It's taken a lot of innovation to get it to work. Engineers had to figure out how to keep heat from one chip in the stack from killing the other, decide what functions should go where and how they should be manufactured, keep the occasional bad chip from leading to a lot of costly dud systems, and deal with the resulting added complexities of doing all that at once. ▣ Here are three examples that show not just how 3D chip stacking is done but also what it's good for.