Memory Bits Research Articles

Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory

Ultra-low-power embedded memory is emerging as a key challenge to design systems with stringent energy but relaxed performance constraints like various wireless sensors and Internet-of-Things (IoT) devices. This paper explores the potential of Si/Ge tunnel FETs (TFET) in designing ultra-low power embedded memory bit cells, namely, Static Random Access Memory (SRAM) and embedded Dynamic RAM (eDRAM). A Technology CAD (TCAD)-based model of 22-nm Si/Ge TFET is designed and coupled with mixed-mode circuit simulation. The circuit-level analysis is performed to study the standby power, performance, and robustness characteristics of TFET SRAM and eDRAM. The results are compared with 22 nm FinFET-based design. The analysis shows that at higher performance targets, TFET-based embedded memory consumes higher standby energy; however, the energy-efficiency of TFET is much better when compared at reduced performance targets. Moreover, it is observed that the cell and array level circuit design strategies that exploit unique TFET properties can help improve robustness at low power regimes.

Tunable properties of spin waves in magnetoelastic heterostructure

Full ferroelastic and simultaneously ferroelectric materials are interesting candidates for applications in devices based on multiferroic heterostructures. They should allow for non-volatile and low-power writing of data bits in magnetoelectric random access memories. Moreover, ferroelasticity, in contrast to piezoelectric material, make magnetic information in ferromagnetic film resistant to external fields. As an example for such a system, we have studied the magnetoelastic interaction between a thin ferromagnetic layer of with a full ferroelastic–ferroelectric gadolinium molybdate crystal. We have investigated the influence of spontaneous strain onto magnetic properties of thin ferromagnetic film. Particularly, we have shown by Brillouin spectroscopy, that it is possible to modulate surface spin wave frequency of by spontaneous strain of gadolinium molybdate substrate.

Effective Hamiltonian for surface states of Bi2Te3 nanocylinders with hexagonal warping

The three-dimensional topological insulator differs from other topological insulators in the family in that the effective Hamiltonian of its surface states on a flat semi-infinite slab requires the addition of a cubic momentum hexagonal warping term in order to reproduce the experimentally measured constant energy contours. In this work, we derive the appropriate effective Hamiltonian for the surface states of a cylinder incorporating the corresponding hexagonal warping terms in a cylindrical geometry. We show that at the energy range where the surface states dominate, the effective Hamiltonian adequately reproduces the dispersion relation obtained from a full four-band Hamiltonian which describes both the bulk and surface states. As an example application of our effective Hamiltonian, we study the transmission between two collinear cylinders magnetized in different directions perpendicular to their axes. We show that the hexagonal warping term results in a transmission profile between the cylinders which may be of utility in a multiple state magnetic memory bit.

ChemInform Abstract: CPP Magnetoresistance of Magnetic Multilayers: A Critical Review

AbstractReview: 380 refs.

Chirality-Dependent Transmission of Spin Waves through Domain Walls.

Spin-wave technology (magnonics) has the potential to further reduce the size and energy consumption of information-processing devices. In the submicrometer regime (exchange spin waves), topological defects such as domain walls may constitute active elements to manipulate spin waves and perform logic operations. We predict that spin waves that pass through a domain wall in an ultrathin perpendicular-anisotropy film experience a phase shift that depends on the orientation of the domain wall (chirality). The effect, which is absent in bulk materials, originates from the interfacial Dzyaloshinskii-Moriya interaction and can be interpreted as a geometric phase. We demonstrate analytically and by means of micromagnetic simulations that the phase shift is strong enough to switch between constructive and destructive interference. The two chirality states of the domain wall may serve as a memory bit or spin-wave switch in magnonic devices.

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

Memories that operate in harsh environments, like for example space, suffer a significant number of errors. The error correction codes (ECCs) are routinely used to ensure that those errors do not cause data corruption. However, ECCs introduce overheads both in terms of memory bits and decoding time that limit speed. In particular, this is an issue for applications that require strong error correction capabilities. A number of recent works have proposed advanced ECCs, such as orthogonal Latin squares or difference set codes that can be decoded with relatively low delay. The price paid for the low decoding time is that in most cases, the codes are not optimal in terms of memory overhead and require more parity check bits. On the other hand, codes like the (24,12) Golay code that minimize the number of parity check bits have a more complex decoding. A compromise solution has been recently explored for Bose–Chaudhuri–Hocquenghem codes. The idea is to implement a fast parallel decoder to correct the most common error patterns (single and double adjacent) and use a slower serial decoder for the rest of the patterns. In this brief, it is shown that the same scheme can be efficiently implemented for the (24,12) Golay code. In this case, the properties of the Golay code can be exploited to implement a parallel decoder that corrects single- and double-adjacent errors that is faster and simpler than a single-error correction decoder. The evaluation results using a 65-nm library show significant reductions in area, power, and delay compared with the traditional decoder that can correct single and double-adjacent errors. In addition, the proposed decoder is also able to correct some triple-adjacent errors, thus covering the most common error patterns.

Statistical yield improvement under process variations of multi-valued memristor-based memories

Memristor, the missing fourth element predicted by L. Chua, has recently been in the research focus since HP Lab reported the first TiO2 thin film memristor realization. The nano-scale geometry size of the memristor makes it difficult to control its dimensions due to the process variation incurred in the fabrication process. This process variation results in yield degradation in the memristor-based memories. This yield degradation is more severe when the memristor device is used as a multi-valued memory element. In this paper, the impact of the process variation on the memristor-based memory yield is investigated for the 1-bit, 2-bit, and n-bit memristor memory element. In addition, two approaches are proposed to improve the memory yield. Therefore, the main objective of this work is to introduce a statistical yield simulation flow to calculate the memory statistical yield under process variations and investigate the effect of different design knobs on this statistical yield regardless of the memristor models and the process variation models used. Simulation results reveal that for 1-bit memristor-based memories, the nominal write voltage should be increased by 30% and the nominal threshold value (i.e., the midway memristance value between the memristor ON resistance and the memristor OFF resistance) should be increased by 65% to achieve the maximum yield. Finally, the paper lists the minimum memristor size that should be used to achieve a 99.9% memory yield for n-bit memories. These results show how the process variation imposes limitations on the minimum memristor device size when multi-valued memories are to be designed.

Experimental test of Landauer's principle in single-bit operations on nanomagnetic memory bits.

Minimizing energy dissipation has emerged as the key challenge in continuing to scale the performance of digital computers. The question of whether there exists a fundamental lower limit to the energy required for digital operations is therefore of great interest. A well-known theoretical result put forward by Landauer states that any irreversible single-bit operation on a physical memory element in contact with a heat bath at a temperature T requires at least k B T ln(2) of heat be dissipated from the memory into the environment, where k B is the Boltzmann constant. We report an experimental investigation of the intrinsic energy loss of an adiabatic single-bit reset operation using nanoscale magnetic memory bits, by far the most ubiquitous digital storage technology in use today. Through sensitive, high-precision magnetometry measurements, we observed that the amount of dissipated energy in this process is consistent (within 2 SDs of experimental uncertainty) with the Landauer limit. This result reinforces the connection between "information thermodynamics" and physical systems and also provides a foundation for the development of practical information processing technologies that approach the fundamental limit of energy dissipation. The significance of the result includes insightful direction for future development of information technology.

Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

Bit failure events induced by random telegraph noise (RTN) for silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells were characterized by directly monitoring the storage node voltage of individual cells, using a device-matrix-array (DMA) test element group (TEG). Correlating the cell-level RTN and failure waveforms with the RTN waveforms of individual transistors that constitute the same cell, RTN of a specific transistor that causes the cell failure was identified.

Dynamic Hardware Monitors for Network Processor Protection

The importance of the Internet for society is increasing. To ensure a functional Internet, its routers need to operate correctly. However, the need for router flexibility has led to the use of software-programmable network processors in routers, which exposes these systems to data plane attacks. Recently, hardware monitors have been introduced into network processors to verify the expected behavior of processor cores at run time. If instruction-level execution deviates from the expected sequence, an attack is identified, triggering processor core recovery efforts. In this manuscript, we describe a scalable network processor monitoring system that supports the reallocation of hardware monitors to processor cores in response to workload changes. The scalability of our monitoring architecture is demonstrated using theoretical models, simulation, and router system-level experiments implemented on an FPGA-based hardware platform. For a system with four processor cores and six monitors, the monitors result in a 6 percent logic and 38 percent memory bit overhead versus the processor’s core logic and instruction storage. No slowdown of system throughput due to monitoring is reported.

Spin-Controlled Conductivity in a Thiophene-Functionalized Iron-Bis(dicarbollide)

The relationship between spin state and conductivity is studied for a thiophene-functionalized iron(III)-bis(dicarbollide) with one or two thiophenes at each end of the cage. Iron has a high ground state spin that can be adjusted by external electromagnetic fields to produce different magnetic states. The hypothesis explored here is that changes in the spin state of these Fe-containing molecules can lead to significant changes in molecular conductivity. Two examples of the possible application of such spin-dependent conductivity are its use as a molecular switch, the basic building block in digital logic, or as a memory bit. The molecules were first optimized using the Becke-3 Lee–Yang–Parr functional (B3LYP) with the 6-31G(d) basis set. A relaxed molecular geometry at each spin state was then placed between gold electrodes to conduct spin-polarized electron transport calculations with the density functional theory/non-equilibrium Green’s functions formalism. The revised Perdew–Burke–Ernzerhf solids exchange–correlation functional (PBES) with double zeta polarized basis set was used. The result of these calculations show that the conductivity increases with the spin state. The cage structure is shown to exhibit fully delocalized molecular orbitals (MOs) appropriate for high conductivity and thus, in this system, the conductivity depends on the position of the MOs relative to the Fermi level. Minority spins are responsible for the conductivity of the doublet spin state while majority spins dominate for the quartet and sextet spin states as they are found closer to the Fermi level when they are occupied. Energy calculations predict a difference in energy between the more and the less conductive spin states (sextet and doublet respectively) that is 15–20 times greater than the thermal energy, which would imply stability at room temperature; however, the energy difference is sufficiently small that transitions between spin states can be induced.

Response to “Comment on ‘Zero and negative energy dissipation at information-theoretic erasure”’

We prove that statistical information theoretic quantities, such as information entropy, cannot generally be interrelated with the lower limit of energy dissipation during information erasure. We also point out that, in deterministic and error-free computers, the information entropy of memories does not change during erasure because its value is always zero. On the other hand, for information-theoretic erasure - i.e., "thermalization" / randomization of the memory - the originally zero information entropy (with deterministic data in the memory) changes after erasure to its maximum value, 1 bit / memory bit, while the energy dissipation is still positive, even at parameters for which the thermodynamic entropy within the memory cell does not change. Information entropy does not convert to thermodynamic entropy and to the related energy dissipation; they are quantities of different physical nature. Possible specific observations (if any) indicating convertibility are at most fortuitous and due to the disregard of additional processes that are present.

Rendezvous with constant memory

We study the impact that persistent memory has on the classical rendezvous problem of two mobile computational entities, called robots, in the plane. It is well known that, without additional assumptions, rendezvous is impossible if the entities are oblivious (i.e., have no persistent memory) even if the system is semi-synchronous (SSynch). It has been recently shown that rendezvous is possible even if the system is asynchronous (ASynch) if each robot is endowed with O(1) bits of persistent memory, can transmit O(1) bits in each cycle, and can remember (i.e., can persistently store) the last received transmission. This setting is overly powerful.In this paper we weaken that setting in two different ways: (1) by maintaining the O(1) bits of persistent memory but removing the communication capabilities, a setting we call finite-state (FState); and (2) by maintaining the ability of transmitting O(1) bits and remembering the last received message, but removing the ability of an agent to remember its previous activities, a setting we call finite-communication (FComm). Note that, even though its use is very different, in both settings, the amount of persistent memory of a robot is a constant number of bits.We investigate the rendezvous problem in these two weaker settings. We model both settings as a system of robots endowed with visible lights, each with a constant number of colors: in FState, a robot can only see its own light, while in FComm a robot can only see the other robot's light. Among other things, we prove that, with rigid movements, finite-state robots can rendezvous in SSynch, and that finite-communication robots are able to rendezvous even in ASynch. All proofs are constructive: in each setting, we present a protocol that allows the two robots to rendezvous in finite time.

An FPGA stereo matching unit based on fuzzy logic

Stereo matching is one of the most used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and recognition, detection and three-dimensional reconstruction of objects. In order to improve the performance, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this paper an FPGA stereo matching unit based on fuzzy logic is described. The proposed algorithm consists of three stages. First, three similarity parameters inherent to each pixel contained in the input stereo pair are computed. Then, the similarity parameters are sent to a fuzzy inference system which determines a fuzzy-similarity value. Finally, the disparity value is defined as the index which maximizes the fuzzy-similarity values (zero up to dmax). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280 × 1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand compared to other FPGA-based stereo matching algorithms: near to 72.35% for logic units and near to 32.24% for bits of memory. In addition, the developed FPGA architecture increases the processing speed: near to 34.90% pixels per second and outperforms the accuracy of most of real-time stereo matching algorithms in the state of the art.

Regenerative memory in time-delayed neuromorphic photonic resonators

We investigate a photonic regenerative memory based upon a neuromorphic oscillator with a delayed self-feedback (autaptic) connection. We disclose the existence of a unique temporal response characteristic of localized structures enabling an ideal support for bits in an optical buffer memory for storage and reshaping of data information. We link our experimental implementation, based upon a nanoscale nonlinear resonant tunneling diode driving a laser, to the paradigm of neuronal activity, the FitzHugh-Nagumo model with delayed feedback. This proof-of-concept photonic regenerative memory might constitute a building block for a new class of neuron-inspired photonic memories that can handle high bit-rate optical signals.

Exploiting data representation for fault tolerance

Incorrect computer hardware behavior may corrupt intermediate computations in numerical algorithms, possibly resulting in incorrect answers. Prior work models misbehaving hardware by randomly flipping bits in memory. We start by accepting this premise, and present an analytic model for the error introduced by a bit flip in an IEEE 754 floating-point number. We then relate this finding to the linear algebra concepts of normalization and matrix equilibration. In particular, we present a case study illustrating that normalizing both vector inputs of a dot product minimizes the probability of a single bit flip causing a large error in the dot product's result. Furthermore, the absolute error is either less than one or very large, which allows detection of large errors. Then, we apply this to the GMRES iterative solver. We count all possible errors that can be introduced through faults in arithmetic in the computationally intensive orthogonalization phase of GMRES, and show that when the matrix is equilibrated, the absolute error is bounded above by one.

A Low Complexity Encoding Algorithm for Systematic Polar Codes

Arikan has shown that systematic polar codes (SPC) outperform nonsystematic polar codes (NSPC). However, the performance gain comes at the price of elevated encoding complexity, i.e., compared to NSPC, the available encoding methods for SPC require higher memory and computation. In this letter, we propose an efficient encoding algorithm requiring only $N$ bits of memory and having $\frac{N}{2}\log_2N$ XOR operations. Moreover, the auxiliary variables in the algorithm can share the memory to reduce extra memory requirement. Furthermore, a parallel 2-bit encoding algorithm is also presented to improve the encoding throughput. Remarkably, we show that parallel encoding can be implemented with the same number of XOR operations and memory bits. Finally, the proposed encoding algorithm can be directly used for NSPC with the same complexity.

Efficient Algorithms for Systematic Polar Encoding

Arιkan has laid the foundations of systematic polar codes and has also indicated that the computational complexity order of the systematic polar encoder (SPE) can be the same of a nonsystematic polar encoder (NSPE) i.e., $\Theta{(N\log N)}$ . In this letter, we propose three efficient encoders along with their full pseudocode implementations, all with $\Theta{(N\log N)}$ complexity. These encoders work for any arbitrary choice of frozen bit indices, and they allow a tradeoff between the number of XOR computations and the number of bits of memory required by the encoder. We show that our best encoder requires exactly the same number of XORs as that of NSPE.

The study of radiation damage of EPROM 2764 memory

A simple statistical theory of radiation damage of semiconductor memory has been constructed. The radiation damage of EPROM memory has been investigated. The measured number of damaged bytes is significantly lower than the expected number resulting from the purely random distribution of the damaged bits. In this way it has been proven that there is a correlation between the failures of individual memory bits which are located in the same byte.

Strain tunability of the downward effective polarization of mechanically written domains in ferroelectric nanofilms

Nano 180° domains written by local mechanical force via the flexoelectric effect have recently attracted great attention since they may enable applications in which memory bits are written mechanically.