Abstract
Ultra-low-power embedded memory is emerging as a key challenge to design systems with stringent energy but relaxed performance constraints like various wireless sensors and Internet-of-Things (IoT) devices. This paper explores the potential of Si/Ge tunnel FETs (TFET) in designing ultra-low power embedded memory bit cells, namely, Static Random Access Memory (SRAM) and embedded Dynamic RAM (eDRAM). A Technology CAD (TCAD)-based model of 22-nm Si/Ge TFET is designed and coupled with mixed-mode circuit simulation. The circuit-level analysis is performed to study the standby power, performance, and robustness characteristics of TFET SRAM and eDRAM. The results are compared with 22 nm FinFET-based design. The analysis shows that at higher performance targets, TFET-based embedded memory consumes higher standby energy; however, the energy-efficiency of TFET is much better when compared at reduced performance targets. Moreover, it is observed that the cell and array level circuit design strategies that exploit unique TFET properties can help improve robustness at low power regimes.
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