4-inch Wafer Research Articles

Bifacial p-Type PERC Solar Cell with Efficiency over 22% Using Laser Doped Selective Emitter

In this paper, we report one bifacial p-type PERC solar cell with efficiency over 22% using laser doped selective emitter produced in larger-scale commercial line on 6-inch mono-crystalline wafer. On front side of the solar cell, square resistance of p-n junction was found to be closely related with laser power at certain laser scan speed and frequency. On the other side, the rear fingers with different ratios of height and width and rear silicon nitride (SiNx) layer with different thickness were optimized, and a highest rear efficiency of the bifacial solar cell was obtained. Finally, bifacial silicon solar cells with the front and rear efficiencies exceeding 22% and 15% (AM1.5, 1000 W/m2, 25 °C) were successfully achieved, respectively.

Wafer-scale transfer-free process of multi-layered graphene grown by chemical vapor deposition

Chemical vapour deposition (CVD) has emerged as the dominant technique to combine high quality with large scale production of graphene. The key challenge for CVD graphene remains the transfer of the film from the growth substrate to the target substrate while preserving the quality of the material. Avoiding the transfer process of single or multi-layered graphene (SLG-MLG) has recently garnered much more interest. Here we report an original method to obtain a 4-inch wafer fully covered by MLG without any transfer step from the growth substrate. We prove that the MLG is completely released on the oxidized silicon wafer. A hydrogen peroxide solution is used to etch the molybdenum layer, used as a catalyst for the MLG growth via CVD. X-ray photoelectron spectroscopy proves that the layer of Mo is etched away and no residues of Mo are trapped beneath MLG. Terahertz transmission near-field imaging as well as Raman spectroscopy and atomic force microscopy show the homogeneity of the MLG film on the entire wafer after the Mo layer etch. These results mark a significant step forward for numerous applications of SLG-MLG on wafer scale, ranging from micro/nano-fabrication to solar cells technology.

Wafer-scale fabrication of high-purity reduced graphene oxide films as ultrahigh-frequency capacitors with minimal self-discharge

Convenient integration of high-purity graphene film on industrial-sized silicon wafer is highly desired for on-chip electronics such as pulse energy harvesting capacitors. However, current graphene materials usually need costly additional purification procedures to remove metallic impurities before use. Herein, a purification-integration technique is explored for graphene oxide (GO) by using the reverse migrations of metal ions and negatively charged GO sheets in water under electric fields, and corresponding films are successfully deposited on 6-inch anodic silicon wafers in one step. Nearly ~90% of metallic impurities (e.g., Fe, Mn, and Cr) could be removed for the electric-field purified reduced graphene oxide film (EPGF) with the content of Cr as low as ~10 ppm. Owing to the high purity and the robust interface contact to silicon substrates, the EPGF as capacitor electrodes delivered the minimal self-discharging current of ~0.11 μA and the highest working frequency of 18420.7 Hz (i.e., up to 10 kHz-level at −73.5°) for graphene capacitors reported to date, as well as maintaining normal areal capacitance. In contrast to the common strategy by increasing ion rate, this study focuses on the improvement of electron rate by optimizing electronic interface contact, which provides new insights for fabricating kilohertz graphene capacitors.

1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor

A 1.2 kV rated 4H-SiC SenseFET structure with monolithically integrated sensing resistor is proposed and experimentally demonstrated. The SenseFET was fabricated on a 6-inch SiC wafer using the same fabrication process as the conventional MOSFET, where Tungsten-Silicided (WSi2) Poly-Si layer was patterned to form the Poly-Si gate and sensing resistor, ${R}_{S}$ , simultaneously. No impact of the integration of the Sense MOSFET and sense resistor on blocking characteristics was confirmed. Good linearity (within ±10%) of the sense voltage with main MOSFET drain current was observed, independent of drain current level, gate bias voltage, and temperature.

Stability Analysis of a Proximate Time Optimal Controlled Electrostatic Suspension System Using Piezo Actuator via Lyapunov Functional Approach

An electrostatic suspension of silicon wafer using proximate time optimal control has been successfully developed. In this system, the movable electrodes which are supplied by constant voltage and actuated by the piezoelectric (PZT) actuator are used instead of stationary electrodes like previous systems. The changing of the gap length between movable electrodes and the suspended object will create varying capacitances that can control the electrostatic forces. To overcome the problem of actuator saturation of the piezo actuator, a proximate time optimal control is used to stabilize the system. The system stability is theoretically investigated using Lyapunov’s function. The constant voltage supplying to the electrode is an important parameter, and it is also determined. The paper presents series of the simulation and experimental results that prove completely suspension of 4-inch silicon wafer without any mechanical contact.

Relationship Between Basal Plane Dislocation Distribution and Local Basal Plane Bending in PVT-Grown 4H-SiC Crystals

The inhomogeneous distributions of basal plane dislocations (BPDs) in PVT-grown 4H-SiC crystal boule due to internal stresses cause lattice plane bending, which strongly affect SiC-based device fabrication. The relationship between BPDs and local basal plane bending in 6-inch 4H-SiC substrates has been investigated. Synchrotron monochromatic beam x-ray topography (SMBXT) imaging shows black and white contrast of BPDs with Burgers vectors of opposite signs based on the principle of ray tracing. We have evaluated the net difference of BPDs with black and white contrast along both [11$$ \bar{2}$$0] and [1$$ \bar{1}$$00] radial directions on the Si face across multiple 6-inch diameter 4H-SiC substrates sliced from the same and different boules and predicted the nature (concave/convex) and amount of bending of the basal plane in these wafers. Line scans of 0008 reflection using high resolution x-ray diffractometry (HRXRD) has been carried out along the two directions to verify the nature of bending in these wafers. Results show quite different bending behavior along [11$$ \bar{2} $$0] and [1$$ \bar{1}$$00] directions, indicating that the Si face of 6-inch substrates creates non-isotropic bending on the basal plane. These observations are correlated quite well with net BPD density analysis. The physical shapes of the wafers were also measured to be not flat due to the surface effect. Quantitative analysis of the degree of basal plane bending based on the SMBXT data was carried out and found to be correlating well with the measured tilt angle from HRXRD. Existence of a high stress center was observed in one of the 6-inch wafers resulting in severe bending which is associated with both large bending angles and abrupt changes in lattice constants a and c.

Facile, wafer-scale compatible growth of ZnO nanowires via chemical bath deposition: assessment of zinc ion contribution and other limiting factors.

ZnO is a highly promising, multifunctional nanomaterial having various versatile applications in the fields of sensors, optoelectronics, photovoltaics, photocatalysts and water purification. However, the real challenge lies in producing large scale, well-aligned, highly reproducible ZnO nanowires (NWs) using low cost techniques. This large-scale production of ZnO NWs has stunted the development and practical usage of these NWs in fast rising fields such as photocatalysis or in photovoltaic applications. The present article shows an effective, simple approach for the uniform, aligned growth of ZnO NWs on entire silicon wafers (sizes 3 or 4 inches), using a low-temperature Chemical Bath Deposition (CBD) technique. In addition to this, a systematic study of the substrate size dependent growth of NWs has been conducted to better understand the effect of the limitation in the deposition rate of Zn2+ ions on the growth of NWs. The growth rate of ZnO NWs is seen to have a strong relationship with the substrate size. Also, the loading efficiency of the Zn2+ ions is higher in ZnO NWs grown on a 3-inch silicon wafer in comparison to those grown on a small piece. An in-depth time dependent growth study conducted on entire 3-inch wafers to track the morphological evolution (length, diameter and number of the NWs) reveals that the growth rate of the length of the NWs reaches a saturation state in a short time span of 20 min. Assessment of the overall homogeneity of the NWs grown on the 3-inch wafer and simultaneous growth on two entire 4-inch silicon wafers has also been demonstrated in this article. This demonstration of large-scale, well-aligned controllable, aligned growth of ZnO NWs on entire silicon wafers is a first step towards NW based devices especially for applications such as photovoltaic, water purification, photocatalysis or biomedical applications.

Prediction Model of Material Removal for Polishing Single Crystal Silicon by Cluster Magnetorheological Finishing with Dynamic Magnetic Fields Based on BP Neural Network

Magnetorheological Finishing (MRF) is a new optical surface processing method, which has the advantages that good polishing effect, no subsurface damage, and suitable for complex surface processing. However, the interaction mechanism between the MRF pad and the workpiece is very complicated, so that the existing MRF material removal theoretical model is not accurate enough to establish the relationship between polishing parameters and material removal. In order to improve the processing efficiency and explore the material removal mechanism, a cluster magnetorheological finishing (CMRF) with dynamic magnetic fields method was proposed. Studying CMRF with dynamic magnetic fields material removal model is helpful to explain the removal mechanism more deeply, and improve the processing efficiency. In this study, the CMRF method was used to conduct a multi-factor orthogonal test on 2-inch single crystal silicon wafers. Based on the empirical Preston equation, the relationship between the machining gap and the polishing pressure was explained. Orthogonal experiments were done for a series of speeds, and obtaining the order of the influence of various factors on the average surface roughness <i>Ra</i> of the workpiece was: workpiece rotation speed > polishing disk speed > magnetic poles rotation speed > oscillating speed; the material removal rate (<i>MRR</i>) was: polishing disk speed > workpiece rotation speed > magnetic poles rotation speed > oscillating speed. Then combining with the orthogonal experimental data, and taking the surface roughness <i>Ra</i> and <i>MRR</i> as evaluation criteria, using Adam (Adaptive momentum) optimization algorithm to build a prediction model of <i>Ra</i> and <i>MRR</i> for polishing single crystal silicon by CMRF with dynamic magnetic fields based on BP neural network. For the prediction result, <i>Ra</i> of the maximum error was 7.05%, the minimum was 0.31%; <i>MRR</i> of the maximum error was 10.22%, the minimum was 1.32%. Therefore, the feasibility of this model for predicting the results of CMRF was verified, and it laid a good foundation for the development of CMRF technology and its industrial application.

Two-dimensional ferromagnetic superlattices.

Mechanically exfoliated two-dimensional ferromagnetic materials (2D FMs) possess long-range ferromagnetic order and topologically nontrivial skyrmions in few layers. However, because of the dimensionality effect, such few-layer systems usually exhibit much lower Curie temperature (TC) compared to their bulk counterparts. It is therefore of great interest to explore effective approaches to enhance their TC, particularly in wafer-scale for practical applications. Here, we report an interfacial proximity-induced high-TC 2D FM Fe3GeTe2 (FGT) via A-type antiferromagnetic material CrSb (CS) which strongly couples to FGT. A superlattice structure of (FGT/CS)n, where n stands for the period of FGT/CS heterostructure, has been successfully produced with sharp interfaces by molecular-beam epitaxy on 2-inch wafers. By performing elemental specific X-ray magnetic circular dichroism (XMCD) measurements, we have unequivocally discovered that TC of 4-layer Fe3GeTe2 can be significantly enhanced from 140 K to 230 K because of the interfacial ferromagnetic coupling. Meanwhile, an inverse proximity effect occurs in the FGT/CS interface, driving the interfacial antiferromagnetic CrSb into a ferrimagnetic state as evidenced by double-switching behavior in hysteresis loops and the XMCD spectra. Density functional theory calculations show that the Fe-Te/Cr-Sb interface is strongly FM coupled and doping of the spin-polarized electrons by the interfacial Cr layer gives rise to the TC enhancement of the Fe3GeTe2 films, in accordance with our XMCD measurements. Strikingly, by introducing rich Fe in a 4-layer FGT/CS superlattice, TC can be further enhanced to near room temperature. Our results provide a feasible approach for enhancing the magnetic order of few-layer 2D FMs in wafer-scale and render opportunities for realizing realistic ultra-thin spintronic devices.

Improving Performances of Enhancement-Mode AlGaN/GaN MIS-HEMTs on 6-inch Si Substrate Utilizing SiON/Al2O3 Stack Dielectrics

Enhancement-mode (E-mode) GaN-based MIS-HEMTs still suffer from undeniable gate leakage or low gate breakdown voltage due to the low quality of gate dielectrics, resulting in a notorious tailing effect of the off-state current. In this letter, a gate scheme featuring SiON/Al2O3 stack dielectrics and partially recessed gate barrier has been employed in the AlGaN/GaN MIS-HEMTs. A high on/off current ratio over $10^{{9}}$ and a small threshold voltage ( ${V} _{\text {th}}$ ) hysteresis less than 20 mV are achieved in the fabricated E-mode devices with a ${V} _{\text {th}}$ around 2.5 V, mainly owing to the reduction of the net positive fixed charge density in the SiON/Al2O3 gate stack confirmed by the ${C}$ - ${V}$ measurements. Meanwhile, a good performance uniformity on 6-inch wafer is achieved which demonstrates the promising scheme for fabricating GaN-based E-mode MIS-HEMT products.

Improved Light Extraction Efficiency of GaN Based Blue Light Emitting Diode Using Nano-Scaled Patterned Sapphire Substrate

In this study, two different conical-shape nano-patterns were fabricated on the 2-inch diameter sapphire wafer in order to improve the efficiency of light-emitting diodes. The conical-shape nano-patterns were fabricated on the sapphire wafer using a nanoimprint technique and dry etching method. A blue LED structure was grown on the nanoscale-patterned sapphire substrates. The photoluminescence and electroluminescence were measured to confirm the effectiveness of the nano-scale patterns. An improvement in the luminescence efficiency was observed in case that nano-patterned sapphire substrate was used; a 1.44 times-higher photoluminescence intensity and a 1.5 times-higher electroluminescence intensity were observed, compared to those of the light-emitting diodes structure grown on a conventional flat sapphire wafer.

Gradient growth of fcc and bcc phase within FexNi1−x (50 < x < 75) films during direct-current wafer electroplating

In order to investigate the performance of Fe-Ni magnetic cores within embedded inductor in 3D package, a series of Fe-Ni films with compositions ranging from 15 wt% to 80 wt% iron were electrodeposited on 8-inch silicon wafer. The uniformity on brightness, phase structure and grain size of Fe-Ni magnetic films were investigated through SEM (scanning electron microscopy) and XRD (X-ray diffraction). A gradient growth behavior of fcc (face-centered cubic) and bcc (body-centered cubic) phase was revealed when Fe content ranges 50–75 wt% within Fe-Ni films, which can be attributed to the slightly faster growth rate of fcc phase. As also revealed in TEM (transmission electron microscope) observation, the fcc phase gradually spread over bcc phase region during the electroplating process, and formed an interface with a slight tilt angle to the substrate on the thickness direction. Several methods, such as increasing solution stirring, temperature or decreasing the current density, were proposed to restrain the gradient growth behavior of Fe-Ni film in wafer level.

Investigation of the distribution of deep levels in 4H-SiC epitaxial wafer by DLTS with the method of decussate sampling

• Z 1/2 defect typically exist in n-type 4H-SiC epitaxial layer. • Defect concentration uniformity of the epilayer is 5.74%. • Z 1/2 defect is uniformly distributed in 4-inch n-type 4H-SiC epitaxial layer. • Ti center did not appear at the temperature range from 80 K to 500 K. In this paper, Schottky structures were fabricated on the epitaxial wafers and the deep levels of the wafers were measured by deep level transient spectroscopy (DLTS). The thickness of the commercial n-type 4°off-axis 4H-SiC (0 0 0 1) epitaxial wafers was 100 μm, with a doping concentration of 2 × 10 14 cm −3 . Nine sample points were selected along with the direction of [1–100] and [11–20] on the wafer. Through the peak fitting analysis of the test results, the detailed information of deep level defects in the epitaxial layer was obtained. The typical deep level defect Z 1/2 was found, but Ti center did not appear, which indicates that Ti center was not introduced in our technological process. Defect concentration uniformity of the 4-inch 4H-SiC epitaxial wafer is 5.74%. The results demonstrate that although the concentration of Z 1/2 defect differs in different locations, but the difference is so small that Z 1/2 defect concentration can be considered to be evenly distributed across the wafer.

Scalable Fabrication of Organic Single-Crystalline Wafers for Reproducible TFT Arrays

Building on significant developments in materials science and printing technologies, organic semiconductors (OSCs) promise an ideal platform for the production of printed electronic circuits. However, whether their unique solution-processing capability can facilitate the reliable mass manufacture of integrated circuits with reasonable areal coverage, and to what extent mass production of solution-processed electronic devices would allow substantial reductions in manufacturing costs, remain controversial. In the present study, we successfully manufactured a 4-inch (c.a. 100 mm) organic single-crystalline wafer via a simple, one-shot printing technique, on which 1,600 organic transistors were integrated and characterized. Owing to their single-crystalline nature, we were able to verify remarkably high reliability and reproducibility, with mobilities up to 10 cm2 V−1 s−1, a near-zero turn-on voltage, and excellent on-off ratio of approximately 107. This work provides a critical milestone in printed electronics, enabling industry-level manufacturing of OSC devices concomitantly with lowered manufacturing costs.

Wafer-Scale Synthesis of Graphene on Sapphire: Toward Fab-Compatible Graphene.

The adoption of graphene in electronics, optoelectronics, and photonics is hindered by the difficulty in obtaining high-quality material on technologically relevant substrates, over wafer-scale sizes, and with metal contamination levels compatible with industrial requirements. To date, the direct growth of graphene on insulating substrates has proved to be challenging, usually requiring metal-catalysts or yielding defective graphene. In this work, a metal-free approach implemented in commercially available reactors to obtain high-quality monolayer graphene on c-plane sapphire substrates via chemical vapor deposition is demonstrated. Low energy electron diffraction, low energy electron microscopy, and scanning tunneling microscopy measurements identify the Al-rich reconstruction ° of sapphire to be crucial for obtaining epitaxial graphene. Raman spectroscopy and electrical transport measurements reveal high-quality graphene with mobilities consistently above 2000 cm2 V-1 s-1 . The process is scaled up to 4 and 6 in. wafers sizes and metal contamination levels are retrieved to be within the limits for back-end-of-line integration. The growth process introduced here establishes a method for the synthesis of wafer-scale graphene films on a technologically viable basis.

Formation of Horizontally and Vertically Oriented MoS2 and MoSe2 Films Using Cracked Small S- and Se-Molecules and Its Applications for Transparent a-Si:H Thin Film Photovoltaic Devices

Molybdenum dichalcogenide films (MoX2, X=S, Se) were fabricated on 6-inch wafers by a breakthrough technique utilizing cracked small X-molecules. Uniformly deposited Mo-metal films were sulfurized or selenized by reactive chalcogen (Xa, a= 1- 2) small molecules, and MoX2 film was approximately 3 times thicker than the Mo metal precursor. The behavior of reaction chamber pressure according to the cracking temperature indicated that one large molecule could crack into 4 – 5 small particles in experimental condition used in this work. The formation of protrusions was also effectively inhibited to obtain MoX2 films of a device quality. First, I will explain how effectively large chalcogen molecules (normally X8) were cracked, and the cracking effect on the film quality. By controlling the cracking temperature separately, we could lower the growth temperature down to 400 oC or lower. The effect of cracking and X-source evaporation temperatures on the film quality will be also presented. The film quality was dependent on the deposition technique of Mo metal films. The films were characterized using x-ray photoelectron spectroscopy (XPS), Raman scattering, atomic force microscopy (AFM), and transmission electron microscopy (TEM). Cross sectional high resolution TEM image, energy-dispersive x-ray spectroscopy, and angle-resolved XPS analysis of 6 nm-thick MoS2 sulfurized at 570 oC showed that the film has well-aligned layer-by-layer crystalline structure and the composition and chemical states were uniform through depth. Normally, layer-by-layer grown MoX2 films on very flat surfaces are studied for device applications as reported in earlier works. But, practical devices require the growth of semiconductor films on rough and/or patterned surfaces. Then, we studied the formation of a few nm-thick and a few tens nm-thick MoX2 films on rough surfaces, and found that the MoX2 films could be successfully grown on a very rough substrate (root mean square roughness = 38 nm) using the method introduced in this work. When MoX2 films were grown by chalcogenizing Mo, the crystalline orientation of MoX2 films depended on the thickness of Mo films. When the Mo film is thinner than 5 nm, we could obtain layer-by-layer structured, i.e., MoX2 films. We had reported the successful application of the horizontally grown MoX2 film to the field effect transistors in the previous work [1]. Contrarily, when the Mo film was 5 nm or thicker, the formed MoX2 films had vertically oriented crystalline structure. It is because the stress due to 3 times volume expansion should be released by changing the crystalline orientation from planar layer-by-layered to vertically oriented structures. In this work, we utilized the vertically oriented MoX2 films as an interlayer between the semiconductor layer and the electrode. By adopting the MoX2 interlayer in amorphous silicon (a-Si:H) thin film photovoltaic devices having the inverted structure, we could obtain greatly improved cell performances. In the substrate type photovoltaic cells, the shunt resistance increased from 10 kΩ (no MoSe2) to 18 kΩ (with MoSe2) and the open circuit voltage increased from 0.717 V to 0.785 V. The a-Si:H photovoltaic cell having 26 % visible light transmittance on a glass substrate showed the conversion efficiency of 7.7 % under blue light irradiation of 7 mW/cm2. In conclusion, the horizontally and vertically oriented MoX2 films of high crystallinity were formed by chalcogenizing Mo metal films using reactive cracked small X-molecules, and the use of MoX2 film as an interlayer greatly improved the performance of a-Si:H thin film photovoltaic devices. The growth method introduced in this work would be one of the most promising methods to obtain uniform and high quality metal dichalcogenide films on a large substrate. The most important advantage of this method is that it can be easily applied to other metal chalcogenide materials. [1] Jung, K. H.; Yun, S. J.; Choi, Y.; Cho, J. H.; Lim, J. W.; Chai, H.-J.; Cho, D.-H.; Chung, Y.-D.; Kim, G. Nanoscale 2018, 10, 15213-15221.

(Invited) Two-Dimensional Layered Materials Toward Phase-Engineered Hybrid Films

2D materials have attracted much attention because of frontier electronic materials due to its superior electronic transport properties and mechanical flexibility in the future, making it a potential material for high performance and wearable electronics. Graphene is a typical 2D materials with high carrier mobility; however, it still cannot be applied in transistor due to the lack of bandgap. A new type of 2D semiconducting materials called transition metal dichalcogenides (TMDCs), which are layered structure with the strong in-plane bonding and weak out-of-plane interactions similar to graphite, have been intensively studied. Recent studies have predicted exceptional physical properties upon reduced dimensionality attracting lots of attention due to the versatile physical chemical behaviors. Nevertheless, the synthesis and the study of the fundamental physical properties of TMDs are still in early stages. The lack of a large-area and reliable synthesis method restrict exploring all the potential applications of the TMDs. Chemical vapor deposition (CVD) is a traditional approach for the growth of TMDs; nevertheless, the high growth temperature is a major drawback for its to be applied in flexible electronics. In this talk, an inductively coupled plasma (ICP) was used to synthesize Transition Metal Dichalcogenides (TMDs) through a plasma-assisted selenization process of metal oxide (MOx) at a low temperature, as low as 250 °C. Compared to other CVD processes the use of ICP facilitates the decomposition of the precursors at lower temperatures; therefore, the temperature required for the formation of TMDs can be drastically reduced. WSe2 was chosen as a model material system due to its technological importance as a p-type inorganic semiconductor with an excellent hole mobility. Large-area synthesis of WSe2 on polyimide (30 x 40 cm2) flexible substrates and 8-inch silicon wafers with good uniformity was demonstrated at the formation temperature of 250 °C as confirmed by Raman and X-ray Photoelectron (XPS) spectroscopy. Furthermore, by controlling different H2/N2 ratios, hybrid WOx/WSe2 films can be formed at the formation temperature of 250 ºC as shown by TEM and confirmed by XPS. The applications including (1) water splitting, (2) gas sensors and (3) photodetectors will be reported.

Multi-wafer batch synthesis of graphene on Cu films by quasi-static flow chemical vapor deposition

The chemical vapor deposition (CVD) of graphene on thin Cu film wafers is highly desirable for the development of technological applications as it offers superior flatness, rigidity, high purity, and compatibility with conventional thin film techniques. Here, we report the high-throughput synthesis of uniform single-layer highly crystalline graphene on a batch of 3-inch wafers. The production throughput is optimized by using closely-packed vertically-standing wafers instead of placing them flat on a horizontal support. Significantly reducing convective gas transport is found to be essential to minimize the variation of graphene single crystal seeding density and growth rate across individual wafers. Given the very small amount of carbon required to grow an atomically-thin layer, we show that graphene can be grown under static gas flow conditions and that the growth rate does not significantly vary from one wafer to another, even within a large batch (∼25 wafers). These findings constitute an important technological step toward the manufacturing of graphene on an industrial scale and its integration into mainstream electronics or micro-electromechanical devices.

High TMR for both in-plane and perpendicular magnetic field justified by CoFeB free layer thickness for 3-D MTJ sensors

We systematically studied the characteristics and influence of free layer thickness in magnetic tunnel junction (MTJ) with a perpendicular synthetic antiferromagnetic (p-SAF) reference layer on 8-inch wafer. The results show clearly that there is an optimal thickness of free layer to achieve the highest tunneling magnetoresistance (TMR) ratio of as high as 80.5% and 53.7% with perpendicular and in-plane magnetic field, respectively, while the resistance-area product (RA) reaches also highest value of 21.1 Ω*μm2. The thickness range of CoFeB to obtain perpendicular magnetic anisotropy (PMA) is determined. The variation of the magnetic moment of free layer indicates that the three-dimensional (3D) sensors can be designed by varying the thickness of the free layer and be controlled by the perpendicular and in-plane components through annealing under the in-plane magnetic field.

Comparative study of different silicon oxides used as interfacial passivation layer (SiNy:H / SiOx /n+-Si) in industrial monocrystalline silicon solar cells

Ultrathin silicon oxide (SiOx) is used as a passivating and tunneling layer in high efficiency passivated contact silicon (Si) wafer solar cells. In this work, the emitter surface passivation quality using a low-cost, low-temperature (40 °C), non-acidic and safe chemical oxide passivation process (named as NCPRE-oxide) grown using sodium hypochlorite solution is compared with other existing oxide growth or deposition processes such as dry thermal oxide, Radio Corporation of America standard clean-2 (RCA-2) chemical oxide, nitric acid based oxide, sulphuric acid based (Piranha) oxide, ozone based oxide and deposited oxide by plasma enhanced chemical vapour deposition on standard 6-inch textured Si wafers. All the oxides layers are capped with hydrogenated amorphous silicon nitride (SiNy:H) improve passivation of the n+-type Si surface. There is a substantial improvement in the effective minority carrier lifetime (τeff) for SiOx/SiNy:H stack on the phosphorous diffused pyramidal textured Si surface. Further, to compare the influence of NCPRE-oxide process with other oxide processes on the electrical performance of the final device, these different processes were included in the fabrication of large area industrial aluminum-back surface field (Al-BSF) solar cells. A comprehensive analysis based on ellipsometry for film thickness measurement, τeff measurement, cell current-voltage characteristics, photoluminescence imaging, internal quantum efficiency mapping, and front surface recombination velocity measurement is presented. The NCPRE-oxide process resulted in a similar improvement in passivation and cell efficiency as other oxide processes for Al-BSF cells. In addition, its low-cost, low thermal budget, easy waste disposal, and single-component nature make it viable for industrial scale implementation.