Wafer-Scale Synthesis of Graphene on Sapphire: Toward Fab-Compatible Graphene.

Neeraj Mishra,Camilla Coletti,Stiven Forti,Clifford Mcaleese,Ilirjan Aliaj,Lars Buß,Filippo Fabbri,Jan I Flege,Bjarke S Jessen,Kenneth B K Teo,Leonardo Martini,Jens Falta,Peter Bøggild,Stefano Roddaro,Ben R Conran,Patrick R Whelan,Abhay Shivayogimath

doi:10.1002/smll.201904906

Abstract

The adoption of graphene in electronics, optoelectronics, and photonics is hindered by the difficulty in obtaining high-quality material on technologically relevant substrates, over wafer-scale sizes, and with metal contamination levels compatible with industrial requirements. To date, the direct growth of graphene on insulating substrates has proved to be challenging, usually requiring metal-catalysts or yielding defective graphene. In this work, a metal-free approach implemented in commercially available reactors to obtain high-quality monolayer graphene on c-plane sapphire substrates via chemical vapor deposition is demonstrated. Low energy electron diffraction, low energy electron microscopy, and scanning tunneling microscopy measurements identify the Al-rich reconstruction ° of sapphire to be crucial for obtaining epitaxial graphene. Raman spectroscopy and electrical transport measurements reveal high-quality graphene with mobilities consistently above 2000 cm2 V-1 s-1 . The process is scaled up to 4 and 6 in. wafers sizes and metal contamination levels are retrieved to be within the limits for back-end-of-line integration. The growth process introduced here establishes a method for the synthesis of wafer-scale graphene films on a technologically viable basis.

Highlights

The route for the implementation of graphene in the electronic/optoelectronic-technology market relies on the existence of a synthesis method that yields graphene films over wafer-scale, with good crystallinity and with contamination levels compatible with large-scale back-end-of-line (BEOL) integration
We identify via low energy electron diffraction (LEED), low energy electron microscopy (LEEM) and scanning tunneling microscopy (STM) measurements the Al-rich reconstruction (√31 × √31)R ± 9° of sapphire to be crucial for obtaining epitaxial graphene
Atomic force microscopy (AFM), and electrical measurements were performed to investigate the quality of the graphene grown with the two different approaches (Fig.1(b)-(g))

Summary

Introduction

The route for the implementation of graphene in the electronic/optoelectronic-technology market relies on the existence of a synthesis method that yields graphene films over wafer-scale, with good crystallinity and with contamination levels compatible with large-scale back-end-of-line (BEOL) integration. Synthesis of graphene on sapphire would provide an alternative route to obtain metal-free graphene that could be transferred onto final target substrates, something that to date has not been achieved at wafer scale for epitaxial graphene on SiC due to the very strong epitaxial interaction with the growth substrate. To date, no work has identified a clear path to obtain wafer-scale metal-free graphene on sapphire with mobilities comparable to those obtained for graphene grown on Cu. Here, we demonstrate and scale up to 4-inch and 6-inch wafers a CVD metal-free approach for growing graphene directly on sapphire substrates that yields films with mobilities above 2000 cm2/Vs and contamination levels compatible with BEOL integration. We perform an in-depth investigation of the graphene/sapphire interface via low energy electron diffraction (LEED) and scanning tunneling microscopy (STM), which allows us to identify the path for high-quality epitaxial growth

Methods

Results

Conclusion