45nm Node Research Articles

Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses

Compute-in-memory (CIM) with emerging non-volatile memories (eNVMs) is time and energy efficient for deep neural network (DNN) inference. However, challenges still remain for DNN in-situ training with eNVMs due to the asymmetric weight update behavior, high programming latency and energy consumption. To overcome these challenges, a hybrid precision synapse combining eNVMs with capacitor has been proposed. It leverages the symmetric and fast weight update in the volatile capacitor, as well as the non-volatility and large dynamic range of the eNVMs. In this article, DNN in-situ training architecture with hybrid precision synapses is proposed and system level benchmarked is conducted. First, the circuit modules required for in-situ training with hybrid precision synapses are designed and the system architecture is proposed. Then, the impact of different weight precision configurations, weight transfer interval and limited capacitor retention time on training accuracy is investigated by incorporating hardware properties into Tensorflow simulation. Finally, the system-level benchmark is conducted at 32nm technology node in the modified NeuroSim simulator for hybrid precision synapse, in comparison with the baseline designs that are solely based on eNVMs or SRAM technology. The benchmark results show that CIM accelerator based on hybrid precision synapse achieves at least 3.07x and 2.89x better energy efficiency for training compared with its eNVM counterparts and SRAM technology at 32nm node, respectively. 227x and 33.8x better energy efficiency are obtained when compared to GPU and TPU. The scaling trend of hybrid precision synapse is projected towards 7nm node and comparison with state-of-the-art 7nm SRAM technology is made.

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

Predictive Modeling for Estimating the Limits for Nonpersistent Effects in MOSFET Response Under Large Signal Gate Injection

In this article, we focus on developing predictive upset models to characterize the nonpersistent effects of large-signal gate-side injection on n-type and p-type metal-oxide semiconductor field-effect transistors ( mosfet s). By “nonpersistent,” we refer to a set of conditions that do not affect the physical characteristics of the device or exhibit any memory effects, i.e., the device will operate normally once the injected large signal stimulus is removed. We present predictive models that determine the maximum limits for large-signal gate-side injection in terms of the device's I ON/ I OFF ratio prior to degradation or damage to the device. A function based on the mosfet technology device parameters, such as its threshold voltage and its power supply rating, is developed and presented. We then validate our predictive models against experimentally measured data for complementary metal–oxide–semiconductor (CMOS) mosfet devices fabricated using 350, 180, 130, and 65 nm standard Taiwan Semiconductor Manufacturing Company (TSMC) CMOS processes. Based on our validated predictive models, we show how the maximum limits for large-signal gate-side injection at 10-MHz change with technology scaling, from ∼9.7 dBm for 350 nm to ∼−1.7 dBm for 65-nm technology nodes for n-type mosfet s; and, from ∼11.0 dBm for 350 nm down to ∼1.2 dBm for 65-nm technology nodes for p-type mosfet s. We anticipate that our predictive models can be leveraged by CMOS circuit designers and electromagnetic interference/compatibility (EMI/EMC) engineers as quick “rule of thumb” guidelines to estimate device and circuit level susceptibility for the injected large signals.

A Study on Three Dimensional Mask Effect of Attenuated Phase‐Shift Mask in Advanced Optical Lithography

Along with the extension of optical lithography to 28nm node and beyond, several effects that can be neglected in previous technology nodes become more and more prominent. One of the most striking effects is the 3D mask effect where the mask transmittance and phase are influenced by the mask topography. This study started with Kirchhoff mask model based experiment of 28nm node SRAM cell features based on Attenuated Phase-shift mask (Att. PSM), which were calibrated into Optical proximity correction (OPC) process models. A 28nm test model was constructed with Kirchhoff mask modeling approach. Once the standard Kirchhoff effects were working on the test wafer, the 3D mask effects were included for the same data. Then the interactive relations among these mask data were investigated and found to generate as much as 15nm edge shift differences. The mask model was then refit including the 3D mask effect and compared with the Kirchhoff mask model in the simulator to better understand the impact of 3D mask effect on patterns.

A Wide Tunable Hysteresis CML Delay Cell for High Frequency

In this letter, a novel high-speed widely tunable voltage-controlled current mode logic (CML) delay cell is implemented in a 65-nm CMOS technology. Variation in the delay of the proposed delay cell is based on the hysteresis control of the output switching threshold by altering the tail current of the CML buffer. The simulation for a single stage cell shows a delay variation of at least 11% in the input clock period at 12.5-GHz clock frequency. While in measurement, the delay line with three stages of the proposed cells shows more than a 38-ps delay variation with an output rms jitter of 1.67 ps for the 9.82-GHz input clock frequency. At this frequency with the highest delay variation, along with additional buffers and delay controllers, the delay line consumes 7.6 mW of power with 1.2-V core supply. The delay line consumes the silicon area of 0.0285 mm2 in the 65-nm technology node.

Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits.

Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.

RF analysis of intercalated graphene nanoribbon-based global-level interconnects

Intercalation doping is emerging as a prospective solution to enhance the performance of graphene nanoribbon interconnects. In this paper, the radio frequency (RF) analysis of stage-2 arsenic pentafluoride- and lithium-doped multilayer graphene nanoribbons (MLGNRs) has been carried out for global-level interconnects in terms of skin depth, surface impedance, critical ratio (CR), transfer gain, and 3-dB bandwidth. The skin-depth results demonstrate that doped MLGNRs exhibit minimum performance degradation primarily due to their higher conductivity, mean free path, and momentum relaxation time as compared to neutral MLGNR. An equivalent second-order accurate RLC model of an intercalation-doped MLGNR has been used to extract the transfer gain and 3-dB bandwidth results at 14-nm technology node for global-level interconnects. The results are further evaluated by implementing an advanced π-type equivalent single conductor derived from multi-conductor transmission line model. The doped MLGNR interconnects demonstrate 11-fold enhancement of 3-dB bandwidth as compared to copper (Cu). Also, the delay and energy-delay-product (EDP) computations in time domain for doped MLGNR interconnects exhibit nearly 10 times lesser delay and significant reduction in EDP than Cu counterparts. It is also observed that optimum values for 3-dB bandwidth and EDP parameters for intercalated MLGNRs could be achieved through width optimization. The RF and transient results validate intercalated MLGNRs as a potential candidate to replace Cu for next-generation global-level interconnects.

BEOL Compatible High-Capacitance MIMCAP Structure Using a Novel High k Material

We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55A film) with minimal leakage current increase compared to Hf based dielectrics, extending the usefulness of MIM on-chip decoupling capacitors. The MIM structure, suitable for BEOL processing is TiN/ZrO2/TiN combined with an anneal which is shown to improve the capacitance vs. leakage performance compared to doped and undoped HfO2 based control structures. GI-XRD measurements demonstrate that the capacitance increase corresponds with a phase transformation of the ZrO2 from amorphous to cubic phase, which is shown to have a dielectric constant (k) up to 35. Reliability models based on hard-breakdown (HBD) show that this structure exceeds the end-of-life targets.Servers and high-performance chips have historically relied on on-chip decoupling capacitors (decap) to reduce power supply noise in order to achieve 3 – 5.4 GHz operating frequency. Although packaging decap can be very effective at mitigating low and mid-frequency noise, on-chip decap, such as MIMCAP, is critical for mitigating mid and high-frequency noise. As Fig. 1 shows, an increase in on-chip decap can result in a significant performance benefit, due to their fast response time slowing the fastest droops, giving time for slower response elements to contribute. One method of achieving this increased decap is to increase the k of the material being used as the insulator in the MIMCAP. Following high-k gate dielectric technology, HfO2 and other Hf based dielectric stacks have been used for this layer successfully [1]. But there is a significant difference in the thermal budget that the dielectric is exposed to following the deposition between gate dielectric and MIMCAP applications. The gate dielectric, deposited prior to any metallization, will typically be exposed to a relatively high thermal budget compared to the insulator layer of a decoupling MIMCAP, which is usually placed between wiring levels in the back end of the line (BEOL) [2]. Since the thermal budget after deposition will affect the crystal structure of a material, and different crystal phases of the same material can have dramatically different dielectric constants [3], the actual dielectric constant of a particular high-k material may vary significantly depending on whether it is used as the gate dielectric or as the MIM insulator. In this work, we explore the use of a ZrO2 as the high- k layer for MIMCAP applications and show that its low crystallization temperature enables it to achieve a significantly higher k value compared to HfO2 when processed under BEOL compatible thermal conditions.Fig. 2 shows the development of the high-k phase of a 55A ZrO2 film as the anneal temperature is increased. The peaks at 35, 42 and 52 are the signature of the bottom TiN electrode and do not change with anneals; but the peaks at 30.2 and 50.3 degrees, which are seen to develop as the anneal temperature increases, match with the 111 and 220 planes of the cubic phase of ZrO2. MIMCAPs built using similarly annealed ZrO2 layers as dielectrics exhibit an increase in capacitance as shown in Fig. 3a: there is a slight increase after anneal A, significantly more increase after anneal B, and additional moderate increases after C and D. No such capacitance increase is seen when Hf based dielectrics are used (Fig. 3b). The maximum capacitance is found to be ~56fF/um2 after anneal D compared to ~43fF/um2 for the unannealed device, an increase of more than 25%, while the leakage current remains virtually unchanged at 1V, and increases by <5x at 2V. Fig. 3c graphs the calculated value of k as a function of the thermal budget, confirming that the ZrO2 layer has the property of crystallizing to its high- k phase at temperatures relatively lower than is typical for HfO2. Thus, we can achieve high capacitance with a relatively thick high-k layer, keeping the leakage current low, all while maintaining compatibility with BEOL processing.[1] T. Ando et al., “CMOS Compatible MIM Decoupling Capacitor with Reliable Sub-nm EOT High-k Stacks for the 7nm Node and Beyond,” Tech. Dig. IEDM 2016, pp. 9.4.1 - 9.4.4.[2] K. Fischer et al., “Low-k Interconnect Stack with multi-layer Air Gap and Tri-Metal-Insulator-Metal Capacitors for 14-nm High Volume Manufacturing,” IEEE Interconnect Tech. Conf. 2015, 10.1109/IITC-MAM.2015.7325600.[3] X. Zhao and D. Vanderbilt, “First-principles Study of Electronic and Dielectric Properties of ZrO2 and HfO2” MRS Proceedings, 747. doi:10.1557/PROC-747-T5.2/N7.2. Figure 1

Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit

Scale down the size of devices introduce the effect of negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) in very-large-scale integration (VLSI) chip design and the major concern is to minimize these effects to a nominal value. In the paper, authors focus in minimization of NBTI effect and develop a noble degradation monitoring sensor circuit named SCHIMOS. A comparison is stated between an analytically strong equisensitive LISOCHIN sensor and SCHIMOS in 90nm and 45nm technology node. Paper experimentally reduces the NBTI effect that is controlled by a number of factors including a reduction in PMOS size, duty cycle, and VDD-Vth tuning. However, NBTI effect degrades the speed and increases the threshold voltage of PMOS transistors. Keywords: NBTI, SCHIMOS, LISOCHIN, PMOS size, VDD-Vth tuning. Cite this Article: Deepjyoti Kalita, Partha Pratim Saikia, Debaprasad Das. Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit. Research &amp; Reviews: A Journal of Embedded System &amp; Applications. 2020; 8(1): 6–11p.

SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

Single-event (SE) performance of the guard-gate flip-flop (GG-FF) and conventional D-FF designs is evaluated at the 16- and 7-nm FinFET technology nodes. The heavy-ion test results show that at the 16-nm node, the GG-FF shows better SE performance for low-linear energy transfer (LET) particles and similar performance for high-LET particles compared with D-FF design. However, at the 7-nm node, the GG-FF shows better SE performance than the D-FF across a wide range of particle LET values. This behavior is due to the higher number of short SE transient (SET) pulses for high-LET particles at the 7-nm node. The heavy-ion test results are used to estimate the number of short SET pulses as a function of particle LET values.

A CNN-Based CMP Planarization Model Considering LDE Effect

As integrated circuit (IC) industry advances to the nanometer scale, layout pattern plays more and more important role on chip fabrication. Layout-dependent effect (LDE) studies how different patterns influence the fabrication results. Chemical–mechanical polishing (CMP), one of the most important processes during IC fabrication, is strongly influenced by LDE. The purpose of this article is to show a convolutional neural network (CNN)-based method to model post-CMP surface topography problem. The method accurately predicts the topological height of the chip surface after CMP by using CNN to abstract features from layout patterns, aiming to analyze defects that may cause failure. This article first addresses about the principles and practicability of using the CNN method to build a CMP model, then builds up a complete CNN structure, and compares the CNN-based model with a traditional pressure-distribution-based CMP model. We designed test chips containing different structures and fabricated them with 28- and 45-nm process nodes. Surface topography is measured using atomic force profiler (AFP) and scanning electron microscope (SEM). The result shows that the total root-mean-squared error (RMSE) of the CNN-based model is 22.41 A, whereas the RMSE of the pressure-distribution-based model is 65.54 A. The CNN-based CMP model shows better accuracy.

High-Voltage Drain-Extended FinFET With a High-${k}$ Dielectric Field Plate

A drain-extended (De) FinFET (DeFinFET) with a high- ${k}$ dielectric field plate is proposed for high-voltage (HV) system-on-chip (SoC) applications at 10-nm CMOS technology nodes. Conventional DeFinFETs without the dielectric field plate and DeFinFETs with SiO2 and HfO2 field plate are investigated by varying the length ( ${L}_{\text {EXT}}$ ) and the doping concentration ( ${N}_{\text {EXT}}$ ) of the fin extension and the thickness ( ${T}_{\text {FOX}}$ ) of the dielectric field plate. The optimized device with the HfO2 field plate has a high breakdown voltage ( ${V}_{\text {BD}}$ ) of 8.56 V, a low specific ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}\_{}{\text {sp}}}$ ) of $6.40~\Omega \cdot \mu \text{m}^{{2}}$ , and a large figure of merit ( ${V}_{\text {BD}}^{{2}}/{R}_{ \mathrm{\scriptscriptstyle ON}\_{}{\text {sp}}}$ ) of 11.46 W/ $\mu \text{m}^{{2}}$ , which are greatly improved HV performance over other devices. This indicates that the HfO2 field plate can effectively address the tradeoff between ${V}_{\text {BD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}\_{}{\text {sp}}}$ . In addition, the excellent electrical characteristics such as high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $3.07\times 10^{-{4}}$ A/ $\mu \text{m}$ , low OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of $6.54\times 10^{-{10}}$ A/ $\mu \text{m}$ , and small subthreshold swing (SS) of 65.54 mV/decade are observed for the optimized HfO2-DeFinFET. Consequently, the proposed design with the high- ${k}$ field plate can be a pathway to realize HV DeFinFETs for SoC technology.

Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation

In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo (MC) simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, MC methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, importance sampling (IS) methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this article, we fill this gap by presenting an efficient mixture IS approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and the higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master–slave latch based on a 28-nm FDSOI process. The results show an improvement in accuracy, resulting in up to $63\times $ better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28-nm technology node.

Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node

In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic, (3) multi-threshold GOTFETs giving both LVT and HVT characteristics by simply altering their terminal connections and (4) line-tunneling-based GOTFETs for analog applications. The most interesting feature of the proposed GOTFET is that in the same device structure, just by changing the material and doping parameters of the device, we can get the optimal performance for different applications. Each of these GOTFET structures have been optimized such that their characteristics are superior than equally sized 45-nm MOSFETs. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. GOTFET characteristics were simulated using industry-standard $$\hbox {synopsys}^{\textregistered }$$ TCAD tools, while the benchmarking with an equivalent CMOS technology was carried out using the standard 45-nm CMOS library in industry-standard $$\hbox {cadence}^{\textregistered }$$ EDA tool. Proposed GOTFETs have minimum on-state currents $$I_{\rm on}$$ at least twice ($$I_{\rm on,GOT} \ge$$$$2I_{\rm on,MOS}$$), with maximum off-state currents $$I_{\rm off}$$ remaining at least an order of magnitude lower ($$I_{\rm off,GOT}$$$$\le 0.1I_{\rm off,MOS}$$), than the corresponding equally sized MOSFETs at the same 45-nm technology node. Circuit analysis and designs are beyond the scope of this paper; however, the innovative GOTFETs proposed in this paper will serve as the basic active devices in digital, ternary logic and analog applications yielding circuit performance far superior to the state-of-the-art designs at the same technology node, as indicated in our previous reports.

Chip Power-Frequency Scaling in 10/7nm Node

The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This article looks at the power-performance benefit of the 10/7nm node as compared to the previous node (14nm). Specifically, we track the power-performance in high performance space, using Intel’s Core-i7 (Intel’s highest performance consumer microprocessor that uses the highest performance CMOS technology node) manufactured in Intel’s 10nm. The paper first looks at the scaling of the device power-performance from the Intel 14++nm node to Intel 10nm, using 3D TCAD simulation with dimensions obtained from actual product cross-sections, and also scaling of the interconnect capacitance node-to-node. Next, the paper does a comparison of industry 10/7nm node technologies (from Intel, TSMC, and Samsung Electronics). The paper argues that for Intel, in the 10nm nodes, the total chip power at constant frequency (energy-per-operation) has scaled by a much lower amount vs. the 14++ node, as compared to the 14++ vs. the previous (22 nm) node. The lack of power scaling can be traced to a reduction in current per device perimeter (caused by the increased device parasitic resistance and the reduced device and fin pitch) and to an increase in capacitance per fin (caused by an increase in the FinFET height). Proper scaling of the device is critical for chip power scaling (energy-per-operation) at upcoming nodes, especially as it applies to high performance microprocessors and for the data analyzed here this is not the case.

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

A 6-nW 0.0013-mm² ILO Bandpass Filter for Time-Based Feature Extraction

Event-driven wake-up sensing methods are emerging functions necessary to increase the autonomy of power-hungry multisensors Internet-of-Things applications. To decrease the power consumption of feature extraction function essential for event-based wake-up, this letter introduces a novel injection-locked oscillator (ILO) filter architecture, to be used in a time-based filter bank for feature extraction. After reviewing the phase shifter property and dynamic behavior of a switched-capacitor injected relaxation ILO, ILO high-pass and bandpass filter designs and transfer functions are presented, resulting in the implementation of a four-channel ILO filter bank in a 65-nm CMOS technological node. Experimental measurements demonstrate the ILO bandpass filtering function works at a power consumption of 6 nW, an active area of 0.0013 mm2 and an output dynamic range of 46 dB. The filter bank average power consumption reaches 3 nW/channel for a total bandwidth from 130 Hz to 5.5 kHz.

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart – when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former’s better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

Ultra Miniature 1850 μm 2 Ring Oscillator Based Temperature Sensor

Temperature sensing is a necessity in semiconductor products, in order to monitor die behavior and avoid thermal runaway, while achieving high performance. Integrated sensors are used to monitor and regulate numerous hot spots across the die to prevent reliability issues. As the hot spots are in the most congested areas of the chip, it is also desirable for the sensors to have a very small sensing element which can be placed close to the hot-spot. The sensors are also used to monitor the coldest parts of the chip to determine the required Vdd level. These functions require the sensors to be very compact as well as low energy. A ring oscillator based temperature sensor is presented in TSMCs 65nm node, with an area of 1850μm 2 . This sensor has a novel structure which is similar to a bandgap reference, with the BJT devices replaced by scaled ring oscillators. The sensor exhibits a 3-sigma inaccuracy of ±1°C near the throttle point, for hot-spot sensing, and ± 2.5°C over the -10°C to 110°C range. The power supply rejection is 2.4°C/V. The sensor consumes 0.94nJ per 10μs conversion and achieves a resolution FOM of 96pJ-K 2 .