Abstract
FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.
Highlights
FinFET transistors with outstanding electrical transport behavior in 14nm CMOS technology have been successfully demonstrated in high-volume production for low power and high performance applications [1]–[4]
Our research indicates the device without lightly doped-drain (LDD) implantation has better characteristics in terms of electrostatistic and Vtsat mismatch, as well as comparable device reliability of hot carrier injection (HCI)
We have studied a full range of device Vtsat flavors from regular (RVT), low (LVT), to super low (SLVT)
Summary
FinFET transistors with outstanding electrical transport behavior in 14nm CMOS technology have been successfully demonstrated in high-volume production for low power and high performance applications [1]–[4]. I. INTRODUCTION FinFET transistors with outstanding electrical transport behavior in 14nm CMOS technology have been successfully demonstrated in high-volume production for low power and high performance applications [1]–[4]. In line with this direction, the experiment was designed to study the LDD-free technology so as to reduce unfavorable scattering degradation, as well as to simplify the process.
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