Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Hyeok Yun,Jun-Sik Yoon,Jinsu Jeong,Rock-Hyun Baek,Hyun-Chul Choi,Seunghwan Lee

doi:10.1109/jeds.2020.3022367

Hyeok Yun, Jun-Sik Yoon + Show 4 more

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https://doi.org/10.1109/jeds.2020.3022367

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Abstract

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Highlights

In this article, by using neural network, we proposed a method to optimize FullyDepleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC)
The enough dataset used to train the neural network model consists of 40,000 pairs of device structure and on/off current ratio for each application
Some optimized values of thickness of buried oxide (Tbox), Lsdj, Lspd, and thickness of source/drain epi (Tsd), determined by neural network, are hard to be considered as the real solution of device structure

Summary

Introduction

By using neural network, we proposed a method to optimize FullyDepleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). The neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. By using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length (Lspd), source/drain junction gradient (Lsdj), and thickness of source/drain epi (Tsd) showed different behaviors for each application and thickness of buried oxide (Tbox) was maximal in optimization results. We proposed a ML method that quickly provides a solution having the maximized Ion/Ioff after the neural networks are trained with maximum 1,000 epochs for each SoC applications: high performance (HP), low operating power (LOP), and low stand-by power (LSTP)

Methods

Findings

Conclusion