Abstract
In this paper, HKMG FDSOI (Fully Depleted Silicon on Insulator) process integration will be presented targeting for 22nm node technology. During the fabrication process, it should be noted that SOI Si loss needs to be well controlled due to FDSOI unique raised-up source and drain feature --- as the remained SOI layer is the seed for epitaxial growth. Spacer formation process plays a significant role on SOI thickness retains. In our work, the using of low k offset spacer SiCN and EPI sacrificial spacer (SiN) is proposed, then two approaches of the spacer formation scheme in FDSOI CMOS process will be demonstrated experimentally --- DDE (dep-dep-etch) and DEDE (dep-etch-dep-etch) scheme. The advantages and drawbacks of each scheme are discussed. Finally, DEDE is chosen for its better sidewall profile.
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