65nm Technology Research Articles

A 28GHz, Switched-Cascode, Class E Amplifier in 22nm CMOS FDSOI Technology

A 28GHz, Switched-Cascode, Class E Amplifier in 22nm CMOS FDSOI Technology

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

A High Gain Concurrent Dual-band Low-Noise Amplifier in 130-nm BiCMOS Technology

This paper presents a fully integrated concurrent 15/30-GHz dual-band low-noise amplifier (LNA). The proposed concurrent LNA IC is designed and simulated in 130-nm BiCMOS technology. The new passive LC notch filter is proposed to realize high gain and low noise figure over dual-band frequency, simultaneously. The simulated BiCMOS LNA IC has exhibited peak gains of 30.1/23.7 dB at 15/30-GHz, respectively, with 20-mW power consumption from 1-V supply. The concurrent dual-band LNA achieves noise figure of 2.2/2.9-dB and IIP3 of -18.2/-8.8 dBm at the respective passbands. Therefore, the proposed dual band concurrent LNA IC is applicable to front-end RF receivers for Ku-Band and Ka-Band systems.

Wire-arc spray directed energy deposition: Correlation of chamber kits refurbishing and particle defects reduction in Ta/TaN thin-film physical deposition processes

Physical Vapor Deposition (PVD) of Tantalum/Tantalum Nitride (Ta/TaN) liner and barrier plays a crucial role in the copper-interconnecting part of semiconductor manufacturing, and this is used for the 130 nm–5nm technology node and beyond. This study focuses on the surface preparation and characterization of wire-arc spray directed energy deposition (DED) coating in the refurbishment process of PVD chamber kits. Spray coating adhesion strength is enhanced due to the pretreatment of the substrate with grit blasting, which creates a suitable surface texture, and the replacement of aluminum alloy as wire-arc spray DED coating material from pure aluminum (99.8%). However, it was experimentally found that using high adhesion strength coating chamber kits increases the probability of out-of-control (OOC) occurrences in the mid-stage of the kit lifetime, and the fundamental reasons may be attributed to the spiky surface morphology of wire-arc spray DED coating layers. Finite element analysis simulates stress distribution and identifies stress concentration regions within the multilayer Ta/TaN thin film using two surface morphologies with significantly different curvature radii of spray coatings. Differences in wire-arc spray DED processing parameters include a slower travel speed, a longer spray time, and a lower feed rate. It is numerically simulated and experimentally observed that coating surface morphology dramatically affects thin film delamination, which is the primary cause of particle defects. This study emphasizes the potential mechanisms for forming particle defects, improved uniformity in spray coatings, and increased surface curvature radius to minimize stress concentration.

Design of a spin–orbit-torque-based self-terminated nonvolatile register for a write/leakage-energy-minimized backup operation

A self-terminated nonvolatile (NV) register that is a key component of a energy-efficient LSI is proposed and its impact on minimizing write and leakage energies during a backup operation before a power-off mode is presented by combining spin–orbit-torque (SOT) devices with CMOS circuitry. The self-terminated NV-register can automatically cut off the write current pulse by continuously monitoring the voltage change due to the state transition of the SOT device. Moreover, the write completion signals can be utilized for a flag whether the circuit can go into the power-off mode which results in the minimization of leakage energy consumption. A case study is performed using a 45nm CMOS technology which results in 71% of total energy reduction in the backup operation compared to that of a typical worst-case design.

Efficient 3’s Complement Circuit for Ternary-ALU

Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.

Modeling the effects of power efficient approximate multipliers in radio astronomy correlators

Large scale Radio Telescopes for Radio Astronomy highly depend on the availability of large (digital) processing capacities for imaging. Estimates concerning power efficiency for future Radio Telescopes lead to anticipated power consumption numbers beyond feasibility. To reduce the power budget, the use of approximate multipliers within the correlator is explored. A baseband equivalent executable model of a radio synthesis telescope is constructed to assess the effects of approximate multipliers. Besides ideal multipliers with floating point accuracy, the use of accurate 8-bit multipliers and 4 different types of approximate multipliers is explored. For each of these multipliers, the energy efficiency of an individual multiplier is known and used to determine the energy efficiency improvement of a correlator when using approximate multipliers. The effects of approximation are quantified by 3 metrics (Signal-to-Noise-Ratio (SNR), Spurious-Free-Dynamic-Range (SFDR) and Root-Mean-Square (RMS) level) derived from maps constructed by the executable model based on an empty sky with only a single point source. This is considered to be the worst case scenario. For illustration purposes, a more realistic input is processed by the model as well. The metrics have been determined based on different SNR levels at the input of each antenna element. For input SNR levels up to 10 dB, all types of approximate multipliers used in this paper can be exploited to improve energy efficiency of correlators, leading to a maximum energy reduction of 19 %. For input SNR values up to 30 dB an energy improvement up to 12 % can be achieved. These percentages are based on implementations in a 40nm low power IC technology at 1 GHz.

Analyzing Performances of Ring Oscillator and Current Starved VCO in 90nm Technology

Analyzing Performances of Ring Oscillator and Current Starved VCO in 90nm Technology

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Background: The global RC interconnects have become the controlling parameter for a circuit’s performance. But with the decrease in technology, an increase in resistance has become prominent. This increase further directly affects the performance of the system by increasing the performance parameters of the circuit like delay and power consumption. To resolve this issue and to be compatible with Internet of Things (IoT) applications, the interconnect circuits are required to be high speed with less heat generation. Methods: In this paper, a new RC and RLC interconnect circuit design was proposed for 45 nm technology to enhance the performance parameters. Furthermore, the RC interconnect design was simulated for lumped and distributed networks. The parasitic component values (resistance, inductance, and capacitance) are evaluated using PTM technology. Results: The proposed interconnect circuit's resistance value decreased by a factor of 4, but the capacitance remains the same. Furthermore, power consumption and delay values were attained. An overall comparison was done between RC and RLC networks. Conclusion: 63.13% power improvement and 24.87% delay improvement were observed in the RLC network over RC distributed network.

Designing and performance analysis of 7 T CNTFET based novel SRAM cell for IoT application

The selection of the title includes designing of SRAM cell using CNTFET because CNTFET overcomes all the issues coming from CMOS technology beyond the 10nm technology node. With the reduction in channel length, the threshold voltage required for CMOS-based technology increases, and the corresponding off-state current decreases. This can prove to be a significant advancement for the semiconductor industry. With the evolution of the new generation of the technology era, especially beyond 10 nm, CMOS is not able to fulfil all the required conditions, as beyond 10 nm technology node, threshold voltage decreases, and consequently off-state current and leakage power increase. This is the reason that CNTFET can be considered a prominent replacement of CMOS transistor for the designing of SRAM cells with the technology node beyond 10 nm. This designed SRAM cell is applicable for IoT applications because IoT uses a microcontroller and the SRAM cell is used as a data memory in the microcontroller. A Data memory always requires high speed, ultra-low power dissipation, and high stability from the cell. Thus, to fulfil this requirement, performance analysis to identify the problem statement of conventional cells and then to improve their performance based on the findings is essential. This is the reason that the 7 T CNTFET-based SRAM novel cell is introduced, and its performance is going to be further improved so that the designed novel cell becomes compatible with IoT applications. Leakage power and stability factor are the main performance parameters to improve of SRAM cells.

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Abstract: Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

In-depth Multi-Objective charge pump design space exploration towards the automatic synthesis of power management units

The inclusion of automation mechanisms in the intricate design of power management units (PMUs) is long pursued in industry. This paper addresses a mixed-signal design flow whose purpose is to automatically produce, from the system-level to the ready-for-tape-out layout, complex PMUs when given a set of specifications. Particularly, in that flow, at the IP level, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from transient analysis for typical and multiple process/temperature corners, must be considered simultaneously. Therefore, it is common for the design cycle of a single integrated charge pump required in a state-of-the-art PMU to surpass a full month, depending on the intended technology, devices’ types and operation voltages. Additionally, by the end of this process, circuit designers often end up with a limited vision of the attainable performances. However, due to the recent improvements in computational power of modern workstations, optimization-based techniques with expensive evaluation mechanisms are now perceived as a potential solution to pursue optimal sizing and layout. Therefore, an academic electronic design automation tool is adapted and applied to explore the performance boundaries of a charge pump in a 180-nm technology node and determine the optimal tradeoffs between performance and the, severely constrained, layout area. In the last step, a worst-case corner optimization on a 45- and 99- dimensional design and performance spaces, respectively, derived from 9 time-consuming transient analysis of each candidate solution, produced 35 design solutions that provide a thorough analysis between worst-case efficiency, voltage drop, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space were used to speed-up the process of devising a solution for tape-out.

Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS

Comparators are an important part of the calculator architecture, and rapid advances in semiconductor and electronics technology have placed higher demands on their performance. Optimization of digital systems involves several levels in order to make improvements in their power consumption, delay, and other parameters. This paper designs a low-power, high speed, and area efficient 4-bit absolute-value comparator, which utilizes a static Complementary Metal-Oxide-Semiconductor (CMOS) and Transmission Gate (TG) hybrid structure. The design optimizes the system at the level of separate circuit blocks, logic gates and transistors. The logic functions are realized by means of transcoding and magnitude Comparison, and the input signals are all driven by two-stage inverters. MUX and XOR with excellent performance of TG structure are implemented using simulation and analysis. In this paper, the transistor sizes and supply voltages of each logic gate are calculated and optimized using MATLAB by applying logic effort theory. The design uses a 65nm technology, and transient simulation of the overall system in Cadence successfully realizes its logic functions with 0.83ns delay and 49.6uw power consumption, proving the effectiveness of the design. This study based on theoretical calculations and simulations is a good reference for the design and theoretical study of very large-scale integrated circuits (VLSI).

DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS

An inverted-T structure is implemented with the Junctionless (JL) topology at nanoscale dimensions. The Inverted-T Junctionless (ITJL) FET features a multi-fin architecture that utilizes the unused space within the fins and combines it with the junctionless topology, maintaining the same doping concentration from source to drain. In order to mitigate the short channel effects and overcome the fabrication challenges, an inverted-T FET has been designed. The crucial performance parameters of device are explored by varying the geometric dimensions and process parameters. The performance of ITJLFET is measured by varying different parameters namely temperature (T), doping concentration (Nd), work function 𝒎 ), and dielectric constant (K) at 30-nm technology node and effect of geometric variations are measured by altering the gate length (Lg) and oxide thickness (Tox). Inverted-T junctionless field effect transistor (ITJLFET) is designed with different gate lengths in the range of 14 nm to 30 nm and shows the improvement in ION by 64% as compared to the conventional JLFET. The parametric analysis like transfer characteristics (Id-Vgs), Ion/IOFF ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL) and gate capacitance (Cgg) are investigated for 250 K to 350 K. From the results, it is perceived that temperature has less effect on the Inverted-T junctionless transistor performance. The cut-off frequency for the designed device is calculated and observed to be in the range of 0.3 to 1.5 THz. Hence, device can be used for high-frequency applications at the submicron regime.

Hardware acceleration of DNA pattern matching using analog resistive CAMs

DNA pattern matching is essential for many widely used bioinformatics applications. Disease diagnosis is one of these applications since analyzing changes in DNA sequences can increase our understanding of possible genetic diseases. The remarkable growth in the size of DNA datasets has resulted in challenges in discovering DNA patterns efficiently in terms of run time and power consumption. In this paper, we propose an efficient pipelined hardware accelerator that determines the chance of the occurrence of repeat-expansion diseases using DNA pattern matching. The proposed design parallelizes the DNA pattern matching task using associative memory realized with analog content-addressable memory and implements an algorithm that returns the maximum number of consecutive occurrences of a specific pattern within a DNA sequence. We fully implement all the required hardware circuits with PTM 45-nm technology, and we evaluate the proposed architecture on a practical human DNA dataset. The results show that our design is energy-efficient and accelerates the DNA pattern matching task by more than 100× compared to the approaches described in the literature.

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

Embedded dynamic random-access memories (eDRAM) are widely used in the design of embedded systems for the safeguard of information during their operation. However, since these memories are installed in the same chip as the host system, it is crucial to consider their dimensioning. For this reason, in our work, the aspect ratio width and length (W/L) of complementary metal oxide semiconductor (CMOS) transistors inside 3-transistor logic cells (3T) is diversified to evaluate the effect on electrical behavior with area optimization through the figure of merit (FoM): power consumption-delay product of 8-bit memories with an operating frequency of 8.3 MHz, varying the aspect ratio of transistors inside the cell have been obtained 8.6f as lowest and 152.3f as highest FoM values. Those storage devices have been developed on 0.00085 mm2 using a 180-nm CMOS technology.

Design and Comparison of SEU Tolerant 10T Memory Cell for Radiation Environment Applications

Single event upsets (SEUs), which are caused by radiation particles, have emerged as a significant concern in aircraft applications. Soft mistakes, which manifest as corruption of data in memory chips and circuit faults, are mostly produced by SEUs. The utilization of SEUs can have both advantageous and detrimental effects in some critical memory applications. Nevertheless, in adherence to design principles, Radiation-Hardening-By-Design (RHBD) methodologies have been employed to mitigate the impact of soft mistakes in memory. This study presents a novel memory cell design, referred to as a Robust 10T memory cell, which aims to improve dependability in the context of aerospace radiation environments. The proposed design has several advantages, including reduced area, low power consumption, good stability, and a decreased number of transistors. Simulations were conducted using the TSMC 65nm CMO technology, employing the Tanner tool. The parameters of the RHB 10T cell were measured and afterwards compared to those of the 12T memory cell. The findings obtained from the simulation demonstrate that the performance of the 10T memory cell surpasses that of the 12T memory cell.

High Speed and Area Efficient Scalable n-Bit Digital Comparator

Abstract: The digital comparator is a crucial design element in various applications, including scientific computations. It is optimized for general-purpose computer architecture, memory addressing logic, queue buffers, and test circuits. High-speed comparators are essential for arithmetic operations, data sorting, and decision-making processes in digital systems. Area efficiency is crucial in integrated circuit design, as it minimizes the physical space a comparator occupies on a chip, reducing manufacturing costs and optimizing performance. The term "scalable" means the comparator can be adapted to handle different word lengths (n-bit), making it versatile for various applications. This project proposes an area-efficient n-bit digital comparator with high operating speed and low-power dissipation. The comparator structure consists of two modules: the Comparison Evaluation Module (CEM) and the Final Module (FM). The CEM involves the regular structure of repeated logic cells used for parallel prefix tree structure, while the FM validates the final comparison based on results from the CEM. The design is implemented using Tanner EDA in 45nm technology