14nm FinFET Technology Research Articles

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

ANN-based framework for modeling process induced variation using BSIM-CMG unified model

In this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as 14nm technology FinFET and 24nm technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (Ioff), on-current (Ion), threshold voltage (Vth), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

Neutron induced single event effects on near-memory computing architecture AI chips

For the near-memory computing architecture AI chip manufactured by using 16 nm FinFET technology, atmospheric neutron single event effect irradiation tests are conducted for the first time in China by using the atmospheric neutron irradiation spectrometer (ANIS) at the China Spallation Neutron Source. During the irradiation, the YOLOV5 algorithm neural network running on the AI chip is used for real-time detection of target objects, including mice, keyboard, and luggage. The purpose of the test is to investigate the new single event effect that may occur on near-memory computing architecture AI chip. Finally, at an accumulated neutron fluence of 1.51×10<sup>10</sup> n·cm<sup>–2</sup> (above 1 MeV), a total of 35 soft errors are detected in 5 categories. Particularly noteworthy is the observation of a new finding, where both computing and memory units experience single event effects simultaneously, which is different from the traditional von Neumann architecture chips. Based on the single event effects that occur simultaneously in these two units, combined with Monte Carlo simulation, a preliminary estimation is made of the physical layout distance between the computing unit and the memory unit on the chip. Furthermore, suggestions are proposed to simultaneously reduce the risk of single event effect in multi cells. This study provides valuable reference and insights for further exploring the single event effects in non-traditional von Neumann architecture chips.

A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology

A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology

Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology

The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined to build both Ripple Carry Adder (RCA) and Carry Save Adder (CSA). The work is carried out using 7nm FinFET technology and this research involves a thorough analysis of power consumption and propagation delay, with the implementation carried out using the Cadence Virtuoso tool. The study highlights the improved performance of 7nm FinFET technology compared to MOSFETs.

A FinFET-based low-power, stable 8T SRAM cell with high yield

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell’s efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at VDD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T.

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset.

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

THE DESIGN OF HIGH EFFICIENCY AND LOW POWER SWITCHED OPAMP

The tendency of design of integrated circuits (ICs) goes to through the power and area reduction way. The surface area of very-large scale integrated circuits is shrinking along with the shrinking of technological dimensions. Power reduction requires usage of low-power design methodologies. The design of Switched-Opamp (SwOp) circuit based on typical Operational Transconductance Amplifier (OTA), with high efficiency is presented. Reduction of power consumption, using digitally controlled switches, is provided. The suggested SwOp was fabricated in a 14nm FinFET technology and achieved a DC gain of 38.4dB, a maximum operating frequency of 11.5GHz and a power consumption of 114.48uW for worst corner (SS) when the load capacitor is 5pF. The power consumption of proposed architecture is reduced about two times. Structure proposed in the paper can be integrated in modern analog-to-digital conversion application, high-speed receivers, memory systems.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Design of Energy-Efficient RFET-Based Exact and Approximate 4:2 Compressors and Multipliers

The ever-increasing demand for low-power and area-efficient circuits for use in battery-powered devices and the CMOS scaling problems have attracted the attention of VLSI designers to beyond-CMOS technologies like Reconfigurable Field-Effect Transistors (RFETs). Improving the efficiency of multipliers is critical as the core component of many applications such as image processing and Machine Learning (ML). This paper proposes a compact and energy-efficient RFET-based architecture for the 4:2 compressor and Dadda multiplier, leveraging transistor-level reconfigurability and multi-input support of the RFET. Moreover, we propose a novel approximate 4:2 compressor based on efficient RFET logic cells to cater to the needs of error-resilient applications. Extensive circuit-level simulations with 14nm germanium nanowire (GeNW) RFET technology show that the proposed RFET-based exact multiplier improves the power consumption and power-delay product (PDP) by 65% and 45%, respectively, compared to the conventional CMOS-based counterpart in 14nm FinFET technology. Besides, we show that utilizing the proposed approximate compressor, the area and PDP of the multiplier reduce by 46% and 42%. The effectiveness of the approximate multiplier is evaluated in the image multiplication, and the average PSNR and SSIM values are 31.39 and 0.87, respectively.

HW/SW Co-Design for Reliable TCAM- Based In-Memory Brain-Inspired Hyperdimensional Computing

Brain-inspired hyperdimensional computing (HDC) is continuously gaining remarkable attention. It is a promising alternative to traditional machine-learning approaches due to its ability to learn from little data, lightweight implementation, and resiliency against errors. However, HDC is overwhelmingly data-centric similar to traditional machine-learning algorithms. In-memory computing is rapidly emerging to overcome the von Neumann bottleneck by eliminating data movements between compute and storage units. In this work, we investigate and model the impact of imprecise in-memory computing hardware on the inference accuracy of HDC. Our modeling is based on 14nm FinFET technology fully calibrated with Intel measurement data. We accurately model, for the first time, the voltage-dependent error probability in SRAM-based and FeFET-based in-memory computing. Thanks to HDC's resiliency against errors, the complexity of the underlying hardware can be reduced, providing large energy savings of up to 6x. Experimental results for SRAM reveal that variability-induced errors have a probability of up to 39 percent. Despite such a high error probability, the inference accuracy is only marginally impacted. This opens doors to explore new tradeoffs. We also demonstrate that the resiliency against errors is application-dependent. In addition, we investigate the robustness of HDC against errors when the underlying in-memory hardware is realized using emerging non-volatile FeFET devices instead of mature CMOS-based SRAMs. We demonstrate that inference accuracy does remain high despite the larger error probability, while large area and power savings can be obtained. All in all, HW/SW co-design is the key for efficient yet reliable in-memory hyperdimensional computing for both conventional CMOS technology and upcoming emerging technologies.

Analytical Modeling of Source-to-Drain Tunneling Current Down to Cryogenic Temperatures

The subthreshold swing (SS) of MOSFETs decreases with temperature and then saturates below a critical temperature. Hopping conduction via the band tail has been proposed as the possible cause for the SS saturation. On the other hand, numerical simulations have shown the source-to-drain tunneling (SDT) current limits the SS at low temperatures. It has been argued which transport mechanism dominates the cryogenic subthreshold current. Hence, for the first time, this paper presents an analytical model of the SDT current and the corresponding SS, which is validated by cryogenic measurement on devices from an advanced 16nm FinFET technology.

Robustness Analysis of 3–2 Adder Compressor Designed in 7-nm FinFET Technology

Adder compressors (ACs) have been employed for several prominent computing datapaths as multipliers, machine learning, discrete transforms, and filters. This brief investigates the robustness of the 3–2 AC against the process, voltage, and temperature (PVT) variability targeting a design for a predictive ASAP7 7nm FinFET technology. The variability impacts on the delay, power, and product-delay-power (PDP) of the 3–2 AC for both super- and near-threshold voltages operating regimes are herein evaluated. Our results demonstrate that process is the main concern among the variability issues for both operating regimes, presenting an even more alarming level of variability in near-threshold operation.

A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

The proliferation of personal artificial intelligence (AI) -assistant technologies with speech-based conversational AI interfaces is driving the exponential growth in the consumer Internet of Things (IoT) market. As these technologies are being applied to keyword spotting (KWS), automatic speech recognition (ASR), natural language processing (NLP), and text-to-speech (TTS) applications, it is of paramount importance that they provide uncompromising performance for context learning in long sequences, which is a key benefit of the attention mechanism, and that they work seamlessly in polyphonic environments. In this work, we present a 25-mm2 system-on-chip (SoC) in 16-nm FinFET technology, codenamed SM6, which executes end-to-end speech-enhancing attention-based ASR and NLP workloads. The SoC includes: 1) FlexASR, a highly reconfigurable NLP inference processor optimized for whole-model acceleration of bidirectional attention-based sequence-to-sequence (seq2seq) deep neural networks (DNNs); 2) a Markov random field source separation engine (MSSE), a probabilistic graphical model accelerator for unsupervised inference via Gibbs sampling, used for sound source separation; 3) a dual-core Arm Cortex A53 CPU cluster, which provides on-demand single Instruction/multiple data (SIMD) fast fourier transform (FFT) processing and performs various application logic (e.g., expectation–maximization (EM) algorithm and 8-bit floating-point (FP8) quantization); and 4) an always-ON M0 subsystem for audio detection and power management. Measurement results demonstrate the efficiency ranges of 2.6–7.8 TFLOPs/W and 4.33–17.6 Gsamples/s/W for FlexASR and MSSE, respectively; MSSE denoising performance allowing 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> smaller ASR model to be stored on-chip with negligible accuracy loss; and 2.24-mJ energy consumption while achieving real-time throughput, end-to-end, and per-frame ASR latencies of 18 ms.

FinFET-based 11T sub-threshold SRAM with improved stability and power

ABSTRACT This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power.

Automated Design of Analog Circuits Using Reinforcement Learning

Analog and mixed-signal (AMS) blocks are often a crucial and time-consuming part of System-on-Chip (SoC) design, primarily due to a manual circuit and layout iterations. Existing automated solutions for selecting circuit parameters for a given target specification are often not efficient, accurate, or reliable. In order for an automated sizing tool to be practical, we posit that it must: 1) return valid results for a large range of target specifications; 2) understand where and why it is unable to meet certain specifications; 3) consider true layout parasitic simulations for complete end-to-end design; and 4) be automated, allowing most of the design effort to fall on the tool. In this article, we address these critical points by establishing an automated reinforcement learning framework, AutoCkt, by 1) successfully deploying it on a complex two-stage transimpedance amplifier and two-stage folded cascode with biasing in the 16-nm FinFet technology; 2) implementing a new combined distribution deployment algorithm to improve efficiency; 3) analyzing in-depth the efficacy of the trained agent; and 4) demonstrating the functionality of this tool when considering a topology that is highly sensitive to layout parasitics. Our algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, up to 38X more efficient than prior work. In addition, our tool averages just four parasitic simulations obtained by using the Berkeley Analog Generator, to achieve a target specification post-layout for the folded cascode. AutoCkt successfully generates LVS-passed designs with validation in process corner variation results.

Analysis of IR Drop, Signal Electromigration and Self-Heating Effect using Flat and Hierarchical Method in FinFET Technology

VLSI industry has been rapidly growing where multiple processors can be implemented on a single chip. In physical design of a chip main factors to be considered are timing closure, congestion, and power. Compare to 180nm and 90nm designs were not much complicated due to less transistor density as going to lower technology nodes chip size, area, length will decrease that impact on packaging and cooling issues, so it is necessary to estimate the power at the early stage of design. Power analysis is done immediately after placement and routing stage of the chip. Power analysis can be performed in two methods one is flat method and other is hierarchical method. In flat method of analysis, the data of both top level and block level is given as input data to calculate the results whereas in hierarchical method of analysis the Power Grid View (PGV) of hierarchical block is designed which is then given as input. In hierarchical runs the sub-blocks are black boxed. The simulation is carried out using the Voltus IC Integrity Solution tool from cadence for a chip designed in 16nm FinFET technology. The results obtained from the flat method of analysis takes 2X the runtime compared to hierarchical method which would be unfavorable for very much larger circuits. The IR drop in VDD and VSS are 11.69 mW and 11.02mW respectively in flat method and 12.32 mW and 13.26 mW for VDD and VSS in hierarchical method of analysis. The accuracy is more obtained in flat run due to its transparency in logic functions.

Temperature-Dependent Threshold Voltage Extraction of FinFETs Using Noise Measurements

In this article, a temperature-dependent threshold voltage extraction method based on noise measurement is proposed. This method induces a mathematical solution for acquiring channel temperatures ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T$ </tex-math></inline-formula> ) of transistors in the saturation region to extract threshold voltages. In order to gain accurate channel temperature, a small-signal equivalent circuit model was established to determine transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ). Then, the extracted transconductance and measured noise power spectral density (NPSD) were used to obtain channel temperatures. On this basis, the temperature-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {th}}$ </tex-math></inline-formula> ) was derived. To validate the reliability of this method, a four-Fin six-finger N-FinFET and a four-Fin eight-finger N-FinFET were fabricated using the 14-nm bulk FinFET technology. In this study, the scattering parameters were obtained from 0.2 to 40.2 GHz. Also, the NPSDs were measured from 1 to 500 Hz, while gate voltage and drain voltage were set as 0.3, 0.49, and 0.75 V. Besides, the transistor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {ds}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {ds}}$ </tex-math></inline-formula> characteristics was also investigated when drain–source bias voltage changed from 0.05 to 0.9 V. Compared with the measurement results, the calculation results of drain–source current model using temperature-dependent threshold voltage achieved higher accuracy. Also, the root mean square errors (RMSEs) were less than 0.60% for four-Fin six-finger N-FinFET and less than 0.51% for four-Fin eight-finger N-FinFET. Therefore, the proposed extraction method can be applied to accurately predict transistor temperature-dependent threshold voltage.

Approximate Recursive Multipliers Using Low Power Building Blocks

Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate results, rather than guaranteeing a correct outcome. Many contributions target the binary multiplier aiming to minimize the complexity of this common yet power-hungry circuit. Approximate recursive multipliers are low-power designs that exploit approximate building blocks to scale up to their final size. In this paper, we present two novel 4×4 approximate multipliers obtained by carry manipulation. They are used to compose 8×8 designs with different error-performance trade-off. The final circuits exhibit a competitive behavior in terms of error while reducing the power dissipation when compared to state-of-the-art proposals. The proposed multipliers and state-of-the-art designs found in the literature, have been synthesized targeting a 14nm FinFET technology to determine the electrical characteristics. Compared with an exact 8×8 multiplier, the least dissipative design proposed in this paper reduces power consumption and silicon area by 46%, and minimum delay by 21%. It also consumes 14% less power than the least power-hungry recursive circuit found in the literature, while offering 81% higher accuracy. Ιmage processing applications and a convolutional neural network are shown to demonstrate the effectiveness of the proposed multipliers.