VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing

S Hwang,R Rajsuman

doi:10.1155/1997/59329

Abstract

In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and IDDQ testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and IDDQ test. Also, the results of IDDQ based test sets (vectors generated specifically for IDDQ testing) are compared with that of stuck-at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridging faults in IDDQ testing.

Highlights

IntroductionThe stuck-at fault model was introduced torepresent faults in digital circuits [1]
Three decades ago, the stuck-at fault model was introduced torepresent faults in digital circuits [1]
We have examined ISCAS-89 sequential benchmark circuits using minimal test sets obtained by GenTest [19]

Summary

Introduction

The stuck-at fault model was introduced torepresent faults in digital circuits [1]. Various techniques have been developed for test generation using this classical fault model It cannot represent some important failure modes directly (including bridging and open faults) [2,3,4], the model is convenient and widely used. In CMOS circuits, many bridging faults cause an output node to be connected to both Vdd and Gnd through low resistance paths, resulting in an indeterminate logic value [6,7]. The potential divider rule dictates that the output in such situations will be in-between high and low voltages. Such fault cannot be detected by conventional logic testing methods, regardless of how the test vector has been obtained

Methods

Results

Conclusion