Abstract
Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in I/sub DDQ/ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG programs. The circuits are simulated with these vectors and power supply current was monitored for bridging faults. A high current state in a faulty circuit is considered as an indicator of fault detection. The test results are given in terms of intra-transistor and gate-level bridging fault coverage. Our results show that stuck-at test vectors can be used very efficiently for I/sub DDQ/ testing of bridging faults, and extra effort to generate specialized test vectors may be unnecessary. >
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