Abstract
This work presents 2D electrostatic potential and threshold voltage modeling of linearly graded work function engineered gate (WFEG) all around (GAA) schottky barrier (SB) MOSFET. Considering suitable boundary conditions across source/channel and drain/channel schottky junctions, Poisson’s equation is solved to derive the potential model of the proposed structure. Threshold voltage expression is then formulated by applying the minimum surface potential concept accordingly. Performance assessment of the present model is demonstrated and compared with conventional SB GAA MOSFET equivalent to establish its superiority in terms of surface potential, threshold voltage degradation and drain induced barrier lowering (DIBL). Comparison with data simulated by ATLAS device simulator is also performed showing accurate agreement between analytical and simulation results.
Published Version
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