Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET

Abstract

Following the ongoing research trend towards the development of nonconventional metal–oxide–semiconductor field-effect transistor (MOSFET) structures to reduce the detrimental influence of various short-channel effects associated with the continual miniaturization of device dimensions through several technology nodes, we have explored a Schottky barrier symmetric double gate (DG) MOSFET incorporating the concepts of gate engineering and dielectric engineering, viz. a work function engineered double gate Schottky barrier MOSFET with high-k gate stack. The study primarily addresses issues related to the source–channel and drain–channel junctions of highly scaled devices by considering metallic source and drain regions to benefit from the barrier height lowering at the metal–semiconductor junctions along with reduced contact resistances, which improves the performance of the proposed device in terms of surface potential, electric field, threshold voltage roll-off, drain-induced barrier lowering, etc. The results obtained from detailed two-dimensional threshold voltage modeling are found to be in excellent agreement with the simulation results, validating the presented analytical model.