A rigorous simulation based study of gate misalignment effects in gate engineered double-gate (DG) MOSFETs

Abstract

The double-gate (DG) Metal–Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) are the front runner among the sub-100nm devices because both front and back gate of DG MOSFETs control the channel region simultaneously. However, alignment between the front and back gate is an issue of concern during fabrication because its influences are baleful for device performance. Further, the issue of alignment between front and back gates assumes greater seriousness for gate engineered DG MOSFETs, like double material double gate (DMDG) or triple material double gate (TMDG) MOSFETs for improving the device performance. In this paper, we present a numerical simulation based study on the effects of gate misalignment between the front and the back gate for gate engineered double-gate (DG) Metal–Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). Both source side misalignment (SSM) and drain side misalignment (DSM) of different lengths in the back gate have been considered to investigate the effects of gate misalignment on device performance. In this context, an extensive simulation has been performed by a commercially available two-dimensional (2D) device simulator (ATLAS™, SILVACO Int.) to figure out the impacts of misalignment on device characteristics like surface potential, threshold voltage, drain-induced-barrier lowering (DIBL), subthreshold swing, subthreshold current, maximum drain current, transconductance and output conductance.