Performance Analysis of Dielectrically Separated Independent Gates Junctionless DG-MOSFET: A Digital Perspective

Abstract

Metal oxide semiconductor field effect transistors (MOSFET) have been downscaled in response to the growing need for small, battery-operated semiconductor devices. However, the existence of significant short channel effect has hindered MOSFET downscaling beyond the nanometer regime. Drain induced barrier lowering (DIBL), velocity saturation, and quantum confinement are examples of these phenomena. To minimize these adverse implications, researchers developed the double gate (DG) MOSFET. Furthermore, the formation of abrupt junctions at deep technological nodes is another barrier to MOSFET downscaling. To solve this problem, junctionless (JL) MOSFETs are used, which have uniform doping in all three areas (Source, Channel, and Drain).For the circuit’s efficient performance, we will use the dielectrically separated independent gates (DSIG) double gate MOSFET. Moreover, from digital IC point of view, logic gates are the basic building blocks and device dimensions play a critical role in their performance. Beyond that, we'll study at how the device dimensions of dielectric separated independent gates (DSIG) JL-DG-MOSFETs impact the behaviour of fundamental logic gates including NOT, NAND, and NOR.