The effects of interlayer dielectric deposition and processing on the reliability of n-channel transistors

Abstract

We report on the effects of interlayer dielectric (ILD) deposition and processing on metal–oxide–silicon field-effect transistor's (MOSFET's) Fowler–Nordheim (FN) stress reliability. The ILD materials examined are plasma-enhanced chemical vapor deposited (PECVD) fluorinated silicon oxide (FSO), PECVD tetra-ethyl- ortho-silicate (TEOS), and spin-on polymer. We used n-MOSFETs with 0.35 μm channel lengths and 90-Å-thick gate oxides as our test vehicles and transistor reliability was assessed using transistor parameter, charge-to-breakdown, and charge pumping measurements. We found out that deposition and processing of the polymer ILD have the least damaging effects on transistor's reliability, whereas deposition and processing of the FSO ILD cause the highest device degradation. We also examined the synergy between damage from ILD deposition and processing and damage from plasma etching by measuring a special test module containing transistors with charging antennae that are sensitive to gate-definition plasma etching. We observed that damage from plasma etching dominates over damage from polymer and TEOS ILD deposition and processing as indicated by the direct correlation between FN reliability and the antenna ratio. However, this was observed not to be the case for damage from FSO ILD deposition and processing which was observed to be as effective as plasma etching damage and to give rise to a “reverse antenna” effect; i.e., the smaller the antenna the less reliable the MOSFET. This is attributed to an interaction which involves plasma charging, fluorine diffusion and defect passivation by fluorine.