New type of dummy layout pattern to control ILD etch rate

Abstract

Adding dummy features (waffles) to drawn geometries of the circuit layout is a common practice to improve its manufacturability. As an example, local dummy pattern improves MOSFET line and space CD control by adjusting short range optical proximity and reducing the aggressiveness of its correction features (OPC) to widen the lithography process window. Another application of dummy pattern (waffles) is to globally equalize layout pattern density, to reduce long-range inter-layer dielectric (ILD) thickness variations after the CMP process and improve contact resistance uniformity over the die area. In this work, we discuss a novel type of dummy pattern with a mid-range interaction distance, to control the ILD composition driven by its deposition and etch process. This composition is reflected on sidewall spacers and depends on the topography of the underlying poly pattern. During contact etch, it impacts the etch rate of the ILD. As a result, the deposited W filling the damascene etched self-aligned trench contacts in the ILD may electrically short to the underlying gates in the areas of isolated poly. To mitigate the dependence of the ILD composition on poly pattern distribution, we proposed a special dummy feature generation with the interaction range defined by the ILD deposition and etch process. This helped equalize mid-range poly pattern density without disabling the routing capability with damascene trench contacts in the periphery which would have increased the layout footprint.