Abstract
A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.
Highlights
Fault simulation is used to determine the effectiveness of a sequence of test vectors in detecting manufacturing faults in integrated circuits
For each fault being considered, the fault vectors of 32 patterns are propagated forward, beginning at the point of the fault and continuing until fault values are no longer different from the good-circuit values. This technique, called parallel pattern single fault propagation (PPSFP) [15], 16] evaluates the matrix row by row, each row corresponding to a different fault
We have developed a new switch-level fault simulator that uses differential fault simulation, to achieve minimum memory requirements and performance overhead, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults
Summary
Fault simulation is used to determine the effectiveness of a sequence of test vectors in detecting manufacturing faults in integrated circuits. Fault parallelism is exploited in parallel fault simulation [5] which evaluates the matrix column by column, where each column corresponds to a different data pattern It uses the computer’s wordlength to simulate many faults in parallel with each bit in the computer word representing the response of the particular faulty circuit. This technique, called parallel pattern single fault propagation (PPSFP) [15], 16] evaluates the matrix row by row, each row corresponding to a different fault It checks whether any row (the faulty values) is identical to the first row (the good values) and drops such a vector from further simulation.
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