Algorithms for fast, memory efficient switch-level fault simulation

Abstract

Abs t rac t A new class of fault simulation algorithms, that have recently been developed for gate-level fault simulation and shown to have several advantages over concurrent fault simulation, are adapted for switch-level fault simulation. High speed compiled switch-level simulation is used for circuit evaluation that approaches the speed of gate-level simulation. The fault simulation algorithms are single fault propagation, differential fault simulation, active fault simulation and parallel active fault simulation. Using these algorithms, minimum memory requirements and high simulation efficiency are achieved, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults.