Switch-level concurrent fault simulation based on a general purpose list traversal mechanism

Abstract

A general-purpose traversal mechanism is described which is used to perform concurrent simulation for complex devices. This traversal mechanism performs all list handling necessary for an accurate and efficient concurrent simulation at a complexity level much higher than that of the gate level. The work on this general-purpose traversal mechanism project has been done within the DECSIM logic simulator. The work to date includes the realization of concurrent MOS fault simulation and the early stage of designing concurrent behavior fault simulation. >