Abstract

A new approach to functional deductive fault simulation is presented in this paper. In this approach, fault models of complex functional digital components are derived using a new modeling technique and a decomposition principle. Also this approach utilizes the deductive technique [AD72] and the fault simulation algorithm is distributed in all the fault models. Every model is independent and is capable of scheduling itself for execution when it receives the input vectors and fault lists at all its input ports. As a result, parallelism may be utilized with relative ease. Functional fault models are also observed to be invariant to their internal implementation and performance measurements indicate that functional fault simulation is significantly faster than gate-level simulation. The CPU time rises linearly with the increasing number of devices simulated as shown by a limited set of experiments. This approach has been verified in the RDV [GS84] at Stanford University.

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