Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Apangshu Das,Sambhu Nath Pradhan

doi:10.1155/2016/3191286

Abstract

The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization.

Highlights

With the rapid increase in the functional complexity and miniaturization of chips, power-density is becoming a critical concern in very-large-scale integration (VLSI) design and synthesis methodologies
The first part concerns the simulation results based on area and powerdensity aware Shared Reed-Muller Decision Diagram (SRMDD) AND-XOR circuits, which proceeded by RTL synthesis of algorithmic resultant circuits using CADENCE “RTL Compiler.”
We have presented a thermal-aware Genetic Algorithm (GA) based heuristic approach for input polarity selection of variables in Shared Reed-Muller Decision Diagram based fixed polarity ANDXOR circuit decomposition

Summary

Introduction

With the rapid increase in the functional complexity and miniaturization of chips, power-density is becoming a critical concern in VLSI design and synthesis methodologies. In this paper, we have proposed a logic synthesizer which tries to optimize the chip area and power-density by providing trade-offs between the two and tries to reduce the thermal effect of the combinational logic circuits. In many real-life circuits used in the fields of coding theory, telecommunication, linear system, computer arithmetic coding circuits, error detectioncorrection circuits, and data encryption and decryption circuits are inherently the basic functions of mod-2 sum form In such cases, AND-XOR minimized algorithms often produce more compact circuit than the AND-OR based realizations. In order to develop an AND-XOR based circuits realization, there are several types of expressions such as positive polarity Reed-Muller (PPRM), fixed polarity ReedMuller (FPRM), pseudo Reed-Muller, generalized ReedMuller, XOR sum of products, and Kronecker and pseudo Kronecker forms [9].

Motivation and Previous Works

Thermal-Aware AND-XOR Problem Formulation and Synthesis Approach

Genetic Algorithm Formulation for SRMDD AND-XOR Network Synthesis

Experimental Results

Conclusion