Abstract

One of the most important challenges of modern ICs is power dissipation, particula-rly the static power dissipation. To be able to reduce static power consumption of an IC, it is separated into different power domains so that the supply power can be turned off for certain domain when not in use. Separate power domains lead to several peculiarities, one of them is the powering up and down the power supply. To represent the supply voltage state by another domain supply, circuits like power sniffers are used. With the evolution of the technologies, the role of random technological variations in the circuits becomes substantial. The paper presents ways to reduce the performance degradation caused by random variations in the 16nm technological process node. HSpice tool is used for circuit simulations. Target sigma representing random variations is 5. For every PVT 300 iterations with random variations are run. The results are presented by QQ plots and measurement table. By applying the proposed modifications performance degradation is reduced by around 40% (average for all measured parameters). By implementing the proposed circuit changes the area of the circuit is increasing by around 35%, no power consumption increase is observed.

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