Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform

Abstract

This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation and leakage current was the main factor for the static power dissipation. The total power dissipation was calculated by the addition of static and dynamic power. From the simulated calculation we found that the consumption of the dynamic power (2.1 mW) was significantly less than the static power (219.75 mW) dissipation and the total power consumption was 221.85 mW. Xilinx-Virtex-II Pro XC2VP30 device is one of the commonly used programmable fabrics, which was employed here for all the calculation.