Abstract
Memory built-in self-test (MBIST) continues to have its unique place in IC industry. It provides test and repair capabilities which significantly increase IC manufacturing yield. In general, the integration of MBIST solutions in a system on chip (SoC) is done via automated flows. Possible issues occurring in the flow should not be skipped as it will degrade the performance of SoC or even may disrupt its functioning. The probability of issues is increased if the SoC has specific structure adding limitations for MBIST solution such as testing the memories by shared interface. Dedicated validation environments (VE) help to overcome these issues. Validation challenges of the MBIST solution via a shared interface for a specific case of multi memory bus BIST engines (MMBBE) are discussed, and a solution is proposed. To avoid the exhaustion increase for the integration scenarios random choices combined with some exhaustions are done depending on a given feature’s priority. Meantime, it is mentioned that for big configurations the usage of random values of parameters might bring to missing some corner cases. Due to that it is recommended to use further some learning methods for reducing the VE iterations and exhaustion within a given iteration. In all the cases, a targeted analysis should be done and decisions should be additionally taken to find out a reasonable number of these iterations. In this paper, a methodology is proposed to soften the mentioned above exhausti-on. A new algorithm of learning is proposed, and the results of the algorithm application are adduced which justify its efficiency in reducing the exhaustion.
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