Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

Abstract

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.