Implementation of Novel High Performance FIR Filter Design Using Wallace Tree Multiplier with 7–3 and 8–3 Compressor

Abstract

AbstractIn this paper, a technique has been proposed for designing of FIR filter using multiplier based on compressor. This proposed FIR filter is simulated and synthesized using Xilinx ISE 14.7 navigator. This technique effectively minimizes the delay. This proposed design of FIR filter has been implemented using (8 * 8) Wallace tree multiplier, with lesser no. of partial products using compressors of different order. Since, this proposed FIR filter design multiplication operation has been obtained in less number of steps as compared to conventional filter. In this, number of stages are reduced from 16-12-8-6-4-3-2. This proposed 8-bit FIR filter with Wallace tree multiplier using 7–3 and 8–3 compressor requires a delay of 4.202 ns and 3.861 ns which is 29% and 34% reduced as compared to the conventional FIR filter. The result also proves that the transistor count has also been reduced to 19%, and power consumption is reduced to 29% with the proposed design, which in turn leads to lesser area consumption for the implementation. Certainly, the function advancement of the proposed multipliers is ratify by implementing a higher order FIR filter using WTM. The result indicates better performance, low latency, and overall efficiency of compressors which can be used for image processing application.KeywordsFIR filterWallace tree multiplierCompressorHigh performanceLatency