High-Performance Wallace Tree Multiplier Design Using Novel 8-4 Compressor Implementation for Image Processing

Abstract

AbstractMultipliers can generate a significant performance in designing filters, MAC units, memories, and image processing applications. Several multipliers have been designed and implemented for various applications. However, the main issue was the latency which is increasing as the number of bits increasing. Multipliers with compressors help in the reduction of latency of partial product which in turn helps in reducing the summation of adders in the final summation stage. In the proposed design of 8 * 8 Wallace tree multiplier, 16 partial products have been obtained by multiplication of operands and multiplicand. In the proposed Wallace tree multiplier design with 8–4 compressor, multiplication operation has been obtained in less number of steps as compared to conventional multiplier without compressors in which the number of stages is reduced from 16-12-8-6-4-3-2. The proposed 8 × 8 Wallace tree multiplier with an 8-4 compressor requires 24.7 ns for completion of the multiplication operation. It thus achieved a 43% reduction in delay as compared to the conventional Wallace tree multiplier (WTM). The simulation result also proves that the proposed design has achieved a 27% reduction in total power dissipation. Thus, the proposed Wallace tree multiplier (WTM) exhibits better interpretation in terms of latency as well as power dissipation, and hence, it can be used for high-performance image processing implementation. The proposed Wallace tree multiplier (WTM) is simulated using ModelSim Student Edition tool and synthesized using Xilinx ISE 14.7 navigator tool.KeywordsWallace tree multiplierCompressorHigh performanceLatency