Abstract
A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.
Highlights
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection
The logic simulator used in PGEN simulates both fault-free and faulty circuits simultaneously, and stops when different values are observed at the output of faulty and fault-free circuits, or when the circuit is simulated for the predefined number of clock cycles
The test generation algorithm described previously was implemented in the program PGEN, which consists of about 5000 lines of C code and runs in a SUN 3/260 environment
Summary
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. The static line walues can be represented by conventional logic and fault models such as logic 1, 0, D,/) [20], while the pulsating line values are represented with the model value P to reflect the circuit behavior in a single and yet compressed time frame For this reason, the name of the proposed test generation method is PGEN (Pulsating Test Generation). The PGEN approach is a compromise between simulation-based and iterative logic array test methods It utilizes the benefits of deterministic test generation methods to ascertain the required input signals for sensitizing and propagating the faults; the search for test patterns is greatly simplified by the pulsating model as will be shown later.
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