Sequential test generators: past, present and future

Abstract

With the growth in complexity of very large scale integration (VLSI) circuits, test generation for sequential circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential test generators. In this paper, we describe and illustrate the working of existing sequential circuit test generation algorithms for the VLSI circuits. We also categorize all sequential testing algorithms, and summarize their relative advantages and disadvantages. The research issues and future directions in the sequential circuit testing area are also discussed.