Sequential test generation at the register-transfer and logic levels

Abstract

The problem of test generation for non-scan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. Our approach is targeted at chips with data-path like STG.The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. Standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in the logic-level implementation. The required state corresponding to the test vector is justified using a fault-free justification step that is performed using the RTL specification. Similarly, if the effect of the fault has been propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification.New and efficient algorithms for fault-free state justification and differentiation on RTL descriptions that contain arithmetic as well as random logic modules are described. Unlike previous approaches, this approach does not require the storage of covers or a partial STG and can be used to generate tests for entire chips without scan. Exploiting RTL information, together with a new conflict resolution technique results in improvements of up to 100X in performance over sequential test generation techniques restricted to operate at the logic level. We have successfully generated tests for the viterbi speech processor chip [18].