Performance Analysis of a Low Power and High Speed Carry Select Adder

Abstract

In microprocessors, digital signal processors, various kinds of arithmetic building blocks such as adder/substractor, multiplier/divider, shifter are required to compute binary data. The priority of datapath can be operation speed, low power consumption, area or design time. The most important design goals in many cases are high operation speed and low power consumption. The basic structure in any arithmetic block is an adder circuit. Hence, by optimising the adder circuit, high oparation speed and low power consumption can be achieved. Several kinds of adders have been proposed to reduce the worst-case propagation delay from Least significant bit(LSB) to Most significant bit(MSB). The Carry select adder is one of the adder architectures that reduces the carry propagation delay by grouping sub-block of adders. Many techiques can be used to improve the CSA performance as proposed by researchers in previous work that is, by using BEC-1(Binary to eccess-1 converter), using D-Latch etc. In this work, the CSA is designed using GDI(Gate diffusion input) technique and using both GDI and MTCMOS D-Latch to achieve betterperformance as compared to previous work. Mentor Graphics 130nm CMOS Technology is used for simulation. The design of CSA using Both GDI and MTCMOS logic achieved a tremendous improvement in operation speed, power consumption and Transistor count of 92.7%, 99.45% and 58.85% respectivelly as compared to the conventional CSA.