GDI based area delay power efficient carry select adder

Abstract

In this Era, the signal processing system is widely used. In the digital signal processing system, adder is the basic building block of all the major circuits. Today the requirements for minimizing the delay, area, and power of adder circuit improve the efficiency of whole system which drives the technology to the next level. Even though the Carry Select Adder (CSLA) occupies more area, it is been used instead of ripple carry adder to avoid propagation delay. In other models Binary to Excess-I Converter (BEC) based Carry Select Adder was also used which uses less number of logic resources than conventional CSLA. But these CSLAs are not more efficient because it rejects one sum after the calculation. So the delay was not more effectively reduced. In order to overcome this problem the reduced logic CSLA is used. But by using Gate Diffusion Input (GDI) Technique can give less delay than this recently proposed reduced logic CSLA. The proposed technique provides low power consumption, less propagation delay. By using this GDI based CSLA the number of transistors required for the circuit also minimized. So an efficient adder design can be achieved through this technique.