GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

Abstract

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.