A Novel Approach to Design Area Optimized, Energy Efficient and High Speed Wallace-Tree Multiplier Using GDI Based Full Adder

Abstract

Design of area optimized very high speed circuits less power utilization is a major concern for the VLSI (very large scale integration) circuit designers. Most of the arithmetic operations are performed using multiplier, which is the more power utilizing block in the digital circuits. In this paper, GDI (Gate Diffusion Input) logic is used to design a full adder in order to achieve low power consumption, optimized area and high speed 16-bit Wallace-tree multiplier. Wallace-tree multiplier designed using GDI logic need less number of transistors; substantially dissipate less power consumption as compare to conventional CMOS logic. The design is synthesized using LT-Snice tool.