Novel partially depleted SOI MOSFET for suppression floating-body effect: An embedded JFET structure

Abstract

Silicon-on-insulator (SOI) devices have an inherent floating body effect which may cause substantial influences in the performance of SOI devices and circuits. In this paper we propose a novel device structure to suppress the floating body effect by using an embedded junction field effect transistor (JFET). The key idea in this work is to provide a path for accumulated holes to flow out of the body to improving of electrical performance. We have introduced a p+-Si1−xGex buried region under the n+-Si1−xGex source and called the proposed structure as embedded JFET SOI MOSFET (EJFET–SOI). Using two-dimensional two-carrier simulation, the output and subthreshold characteristics of EJFET–SOI are compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the EJFET–SOI structure as expected without consuming a significant amount of area.