Modeling and testing for stuck faults in BiCMOS combinational circuits

Abstract

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) and parametric behavior of the BiCMOS circuits in the presence of transistor stuck faults. The model employs the logic transistor function (LTF). The LTF describes the circuit in terms of its input variables and transistor topology. The model assumes four logic values: 0, 1, M and I, where M and I imply a memory and an indeterminate element, respectively. The faults in BiCMOS circuits may affect the logic level at the output or the parameters of the circuit. The circuits are normally tested at the parametric level by IDDQ (steady state power supply current) testing or by timing testing. The LTF model is utilized to generate the test vectors for both the functional testing and the parametric testing. Simulation is performed using hspice to support the results.