Abstract
A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition‐once logic, clock gating, and others.
Highlights
INTRODUCTIONLow power design is mainly driven by the need to contain power dissipation ( reduce packaging and cooling costs) for high-performance systems at one end of the applications spectrum and by the desire to reduce power consumption ( reduce size, weight and increase battery life) for portable applications at the other end
Low power design is mainly driven by the need to contain power dissipation for high-performance systems at one end of the applications spectrum and by the desire to reduce power consumption for portable applications at the other end
Depending on where gating is applied in the clock tree we considered the following three cases: top clock gating at the top level of the tree, flat clock gating only at the leaf level of the tree, hierarchical clock gating where gating is done both at the leaf level and at higher levels in the tree based on typing information
Summary
Low power design is mainly driven by the need to contain power dissipation ( reduce packaging and cooling costs) for high-performance systems at one end of the applications spectrum and by the desire to reduce power consumption ( reduce size, weight and increase battery life) for portable applications at the other end. This paper presents several low power techniques used in the design of an ASIC DSP core for portable applications. Both dynamic power (in active mode), and static power (in standby mode), are critical and need to be addressed for batteryoperated devices
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