Abstract
While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware support environment for application-specific systems is described which provides a designer with a set of hardware modules and circuitry, that support these standards and software tools for automatic incorporation of testability hardware, as well as automatic test vector and test program generation.
Highlights
While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more testable, diagnosable, and maintainable
The work reported in this paper automates the process of incorporating testability into the SIERA design system, it provides dedicated hardware and software for controlling the test circuitry that has been added to each level of the system’s hierarchy
The text hardware incorporation was automated by hardware module generators
Summary
A prototype chip called TEST_CHIP1 has been implemented in 2u CMOS technology using the MOSIS fabrication facility. In this hierarchy, each chip contains a Boundary Scan interface; all Boundary Scan devices on each board are serially cascaded forming a single scan path where all of the control and test data are applied through a centralized Boundary Scan slave interface; all Boundary Scan slave interfaces on every board are tied to the Boundary Scan master interface on the Test Master Controller board, where test programs direct the execution of all test functions for the entire system; at the level, the CPU board is used to initialize the Test Master Controller board, which is described ; and at the top-most level, the UNIX workstation provides the user interface for the Test and Diagnosis system where test vectors are automatically generated and test results are analyzed. It can be dynamically reconfigured to suport other testability bus standards that use a 5 wire serial test access port
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