Abstract
Compared to the silicon power devices, silicon carbide device has shorter switch time. Hence, as a result of the faster transition of voltage (dv/dt) and current (di/dt) in SiC MOSFET, the influence of parasitic parameters on SiC MOSFET’s switching transient is more serious. This paper gives an experimental study of the influence of parasitic inductance on SiC MOSFET’s switching characteristics. Most significance parameters are the parasitic inductances of gate driver loop and power switching loop. These include the SiC MOSFET package’s parasitic inductance, interconnect inductance and the parasitic inductance of dc link PCB trace. This paper therefore focuses on analysis and comparison of different parasitic parameters under various operation conditions in terms of their effect on overvoltage, overcurrent and switching power loss.
Highlights
Power semiconductor devices are attracting increasing attention as key components in a variety of power electronic systems
At time t0, the SiC MOSFET which is the device under test (DUT) is turned on
According to the loop concept, for the stray inductances’ parameters to be studied, the network’s stray inductance can be narrowed down to three primary lumped inductances according to the current paths. 1) the gate loop inductance, LG, formed by the gate current path, where Lg= Lg1+Lg2; 2) the main switching loop inductance, Ld, formed by the drain current path, which includes the stray inductances of the MOSFET and Diode packages as well as PCB interconnections, Ld=Ld1+Ld2+Ld3+Lb1+Lb2; 3) the common source inductance LS that exists in both loops, which can be treated as a mutual inductance between the gate loop and the switching loop
Summary
Power semiconductor devices are attracting increasing attention as key components in a variety of power electronic systems. Electromagnetic oscillation may occur due to the interaction between the voltage and current transitions with the circuit stray inductance and capacitance This may increase switch losses as well as contributing to electromagnetic interference problems. A few studies on the influence of parasitic parameters on SiC power MOSFET switching characteristics have been mentioned. All the gate loop and power switching loop parameters have been independently controlled and studied based on the SiC MOSFET switching characterization test bench. Their influences on SiC MOSFET switching characteristics can be shown from the experimental waveforms. The degree of influence of all parameters have been evaluated in terms of overvoltage, overcurrent and switching loss
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