Hot-carrier effects in deep submicron SOI MOSFETs

Abstract

Hot carrier effects are investigated thoroughly in deep submiron N- and P-channel SOI MOSFETs, for gate lengths down to sub-0.1 μm. In particular, the hot-carrier-induced degradations of these devices are analyzed in the light of photon emission and gate current experiments. It is shown that the hot carriers which lead to the degradation of the main electrical parameters of deep submicron SOI MOSFETs are created by various mechanisms (MOS and/or parasitic bipolar transistor carrier transport) depending on the channel length, the carrier type and the biasing conditions. In this respect, for N-channel SOI devices the worst case for the device lifetime can be either the maximum gate current condition ( V g = V d), or the maximum substrate current condition ( V g ≈ V d 2 ), or the PBT condition ( V g = 0). However, for P-channel devices the maximal transistor aging is always obtained in the case of maximal gate current ( V g = V d).