Hot-carrier effects in deep submicron SOI MOSFETs

Abstract

SOI devices are of great interest, especially for low voltage-low power applications, due to improved isolation, reduced subthreshold slope and parasitic capacitances compared with bulk devices. However, when the devices are scaled down, SOI MOSFETs also suffer from hot-carrier effects (HCE). For the prediction of the long term reliability of MOS devices, the study of hot-carrier injections is necessary. In the case of bulk Si MOSFETs, the relevant operation regimes for HCE are the maximum substrate current (Vg=Vd/2) and the maximum gate current (Vg=Vd) conditions. However, for SOI transistors, hot carriers can also be created by the action of the parasitic bipolar transistor (PBT) which strongly affects the electrical properties in the low gate voltage range (Vg=O-Vt). The aim of this paper is to present, for the first time, a thorough analysis of hot carrier effects in deep submicron SOI MOSFETs, for gate lengths down to sub-0.1 /spl mu/m. The hot carrier degradation of the main electrical properties of these devices obtained for various biasing conditions is evaluated in the light of photon emission and gate current measurements. The N- and P-channel SIMOX MOSFETs used in our experiments are partially depleted (tsi=100 nm), with 4.5 nm gate oxide and 90 nm buried oxide thicknesses.