High-speed CRC design for 10 Gbps applications

Abstract

The use of cyclic redundancy codes (CRCs) in many high-throughput applications has made the design of parallel CRC circuitry an important research topic. Parallel implementation of the linear feedback shift registers (LFSRs) requires multiple input bits being processed at the same time; therefore, is much faster than the serial implementation. The common way to process M input bits simultaneously is to multiply the companion metric M times and put the resulting circuit in the feedback loop. This, however, will increase the circuit complexity within the loop so as to limit the final speedup ratio. In this paper, based on the state-space transformation, we investigate how to design high-speed CRC circuitry for 10 Gbps applications. Our design can efficiently deal with the case that the length of the message bits is not a multiple of M and achieves low-cost solution by sharing the input block with the output block outside the feedback loop.